- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄24827 > 935268252557 (NXP SEMICONDUCTORS) 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144 PDF資料下載
參數(shù)資料
| 型號： | 935268252557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-486-1, LQFP-144 |
| 文件頁數(shù)： | 62/80頁 |
| 文件大小： | 306K |
| 代理商： | 935268252557 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁當前第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁
Philips Semiconductors
Preliminary specification
PDI1394L40
1394 enhanced AV link layer controller
2000 Dec 15
62
13.3.10
Asynchronous RX/TX Interrupt Enable (ASYINTE) – Base Address: 0x0A4
29 28
27 26 25 24 23
22 21 20 19 18
17 16
15 14 13
12 11 10
9
8
7
6
5
4
3
2
1
0
ETIMEOUT
ERCVDRSP
ERRSPQFULL
ERREQQFULL
ERREQQQA
V
ERRSPQRDERR
ERREQQRDERR
ERRSPQQA
V
ESIDQA
V
ERREQQLASTQ
ETRSPQFULL
ERRSPQLASTQ
ETREQQWRERR
ETRSPQWR
ETRSPQWRERR
ETREQQFULL
ETREQQWR
31 30
SV00797
Reset Value 0x00000000
Bits16..0 are interrupt enable bits for the Asynchronous RX/TX Interrupt Acknowledge (ASYINTACK).
13.3.11
RDI Register – Base Address: 0x0B0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11
10
9
8
7
6
5
4
3
2
1
0
SWPD
LPST
A
T
EPLI
ELOA
ESCA
ESCI
SV01779
PLI
LOA
SCA
SCI
NOTE:
1. Also refer to Section 12.5.3 for functional descriptions.
Reset Value 0x00000000
Note: Before asserting the RPL bit, SWPD or setting the PD pin high, the user should assure that the link chip is in
the following state of operation:
1) The isochronous transmit FIFO is not receiving data for transmission
2) The isochronous transmitter is disabled
3) No asynchronous packets are being generated for transmission
4) Both the ASYNC request and response queues are empty
Bit 31:
R/W
SWPD: Software power–down. Writing a 1 to this register bit will cause the link to de–activate its LPS pin causing the
PHY to turn off the SCLK to the link. This, in turn, causes the link chip to go into a low power mode in which only the
RDI register is accessible. The function of this bit is identical to that of the hardware pin ”PD”. When PD is set (1),
SWPD will be set automatically by the pin state and will cause entry into the power down mode as stated above. DO
NOT USE BOTH (HARDWARE AND SOFTWARE) MODES OF OPERATION TO CAUSE THE POWER DOWN
FUNCTION. Use either hardware mode (the PD pin) OR the software method (setting / resetting the SWPD bit), not
both. The PD pin will take precedence over the software method... the link will not come out of PD mode unless the
PD pin is de–asserted (0). An unused PD pin should be connected to the link chip ground. The SWPD bit
does not
indicate the status of the PD pin. See Section 12.5.3 for more information.
Bit 30:
R
LPSTAT: Link – PHY interface status. This bit reflects the status of the LPS signal. When the LPS signal is active
(pulsing) the PHY interprets it as indicating that the link power is on and the link is requesting to be activated. The
PHY, in turn, supplies the SCLK to the link, thus giving it the means to become active. The SCLK is used by the link
to operate most of its internal circuitry. If LPS was active and then de–activated, it is a signal to the PHY chip that the
link desires entry into the power down mode. The LPSTAT bit continually indicates the status of the LPS pin and thus
the overall status of the link – PHY interface. It should also be noted here that a momentary de–activation of the LPS
signal by the setting of the RPL bit (bit 18 of register 0x004, LNKCTL) to cause a link – PHY interface reset will also
be indicated by the LPSTAT bit. It is suggested that this momentary status change be ignored when the host
controller causes a link – PHY reset through the use of the RPL bit.
Bit 19:
R/W
EPLI: Enable the PHY – link initialized interrupt. Leaving this bit in the reset (0) state allows the PLI bit to be read as
a status bit.
Bit 18:
R/W
ELOA: Enable link–on active interrupt. Leaving this bit in the reset (0) state allows the LOA bit to be read as a status
bit.
Bit 17:
R/W
ESCA: Enable SCLK active interrupt. Leaving this bit in the reset (0) state allows the SCA bit to be read as a status
bit.
Bit 16:
R/W
ESCI: Enable SCLK inactive interrupt. Leaving this bit in the reset (0) state allows the SCI bit to be read as a status
bit.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 08008GOB | 125 A, 800 V, SCR, TO-209AC |
| 935268252551 | 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144 |
| 08008GOC | 125 A, 800 V, SCR, TO-209AC |
| 08008GOD | 125 A, 800 V, SCR, TO-208AD |
| 08010GOB | 125 A, 1000 V, SCR, TO-209AC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 935268721125 | 制造商:NXP Semiconductors 功能描述:Buffer/Line Driver 1-CH Non-Inverting 3-ST CMOS 5-Pin TSSOP T/R |
| 935269304128 | 制造商:ST-Ericsson 功能描述:IC AUDIO CODEC W/TCH SCRN 48LQFP |
| 935269544557 | 制造商:NXP Semiconductors 功能描述:SUB ONLY TDA9587-2US1-V1.3 |
| 935269987557 | 制造商:NXP Semiconductors 功能描述:SUB ONLY TDA9587-1US1-V1.8 SUBBED TO 935269987557 |
| 935270713557 | 制造商:NXP Semiconductors 功能描述:SUB ONLY IC CHP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。