參數(shù)資料
型號(hào)： 935268252557
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-486-1, LQFP-144
文件頁(yè)數(shù)： 43/80頁(yè)
文件大?。?/td> 306K
代理商： 935268252557
Philips Semiconductors
Preliminary specification
PDI1394L40
1394 enhanced AV link layer controller
2000 Dec 15
45
13.1
Link Control Registers
13.1.1
ID Register (IDREG) – Base Address: 0x000
The ID register is automatically updated by the attached PHY with the proper Node ID after completion of the bus reset.
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SV00915
NODE ID
BUS ID
VERSION CODE
3130
PART CODE
Reset Value 0xFFFF0301
Bit 31..22:
R/W
BUS ID: The 10-bit bus number that is used with the Node ID in the source address for outgoing packets and used to
accept or reject incoming packets. This field reverts to all ‘1’s (0x3FF) upon bus reset.
Bit 21..16:
R/W
NODE ID: Used in conjunction with Bus ID in the source address for outgoing packets and used to accept or reject
incoming packets. This register auto-updates with the node ID assigned after the 1394 bus Tree-ID sequence.
Bit 15..8:
R
PART CODE: “03” designates PDI1394L40.
Bit 7..0:
R
VERSION CODE: “01” shows this is revision level 1 of this part.
13.1.2
General Link Control (LNKCTL) – Base Address: 0x004
The General Link control register is used to program the Link Layer isochronous transceiver, as well as the overall link transceiver. It also
provides general link status.
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7
6
5 4 3
2 1
0
SV00892
IDV
ALID
RCVSELFID
ROOT
BUSYFLAG
CYTMREN
STRICTISOCH
CYMASTER
CYSOURCE
RST
Tx
RST
Rx
TxENABLE
RxENABLE
BSYCTRL
ATACK
31 30
TxRDY
RPL
DA
T
AINV
L
TLEND
Reset Value 0x46000002
Bit 31:
R/W
IDValid (IDVALID): When equal to one, the PDI1394L40 accepts the packets addressed to this node. This bit is
automatically set after selfID complete and node ID is updated.
Bit 30:
R/W
Receive Self ID (RCVSELFID): When asserted, the self-identification packets, generated by each PHY device on the
bus, during bus initialization are received and placed into the asynchronous request queue as a single packet. Bit 30
also enables the reception of PHY configuration packets in the asynchronous request queue.
Bit 29..27:
R/W
Busy Control (BSYCTRL): These bits control what busy status the chip returns to incoming packets. The field is
defined below:
000 = use protocol requested by received packet (either dual phase or single phase)
001 = RESERVED
010 = RESERVED
011 = use single phase retry protocol
100 = use protocol requested in packet, always send a busy ack (for all packets)
101 = RESERVED
110 = RESERVED
111 = use single phase retry protocol, always send a busy ack
Bit 26:
R/W
Transmitter Enable (TxENABLE): When this bit is set, the link layer transmitter will arbitrate and send packets.
Bit 25:
R/W
Receiver Enable (RxENABLE): When this bit is set, the link layer receiver will receive and respond to bus packets.
Bit 23:
R
Data Invariant (DATAINV) refers to the byte ordering of data being presented to the Link through the host interface
(HIF) port and the handling of the address and data lines by the link chip. When DATAINV = 0, the Link is in address
invariant mode. When DATAINV = 1, the Link is in data invariant mode. This bit is only important if the LTLEND
(Little Endian) bit is set (1), otherwise it is ignored. Interpretation of address and data information varies with the
settings of these bits and with the data format being presented. See the section on Big and Little Endian Modes for
more information (Section 12.5.3).
相關(guān)PDF資料
PDF描述
08008GOB 125 A, 800 V, SCR, TO-209AC
935268252551 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144
08008GOC 125 A, 800 V, SCR, TO-209AC
08008GOD 125 A, 800 V, SCR, TO-208AD
08010GOB 125 A, 1000 V, SCR, TO-209AC
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