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參數(shù)資料
| 型號(hào)： | 935268252557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-486-1, LQFP-144 |
| 文件頁數(shù)： | 46/80頁 |
| 文件大?。?/td> | 306K |
| 代理商： | 935268252557 |
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Philips Semiconductors
Preliminary specification
PDI1394L40
1394 enhanced AV link layer controller
2000 Dec 15
47
13.1.3
Link /Phy Interrupt Acknowledge (LNKPHYINTACK) – Base Address: 0x008
The Link/Phy Interrupt Acknowledge register indicates various status and error conditions in the Link and Phy which can be programmed to
generate an interrupt. The interrupt enable register (LNKPHYINTE) is a mirror of this register. Acknowledgment of an interrupt is accomplished
by writing a ‘1’ to a bit in this register that is set. This action reset the bit indication to a ‘0’. Writing a ‘1’ to a bit that is already “0” will have no
effect on the register.
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SV01840
CMDRST
F
AIRGAP
HDRERR
TCERR
ARBGAP
PHYINT
SNT_REJ
ITBADFMT
A
TBADFMT
PHYRRX
CYTMOUT
PHYRST
CYDONE
CYPEND
CYST
AR
T
CYSEC
CYLOST
31 30
TIMER
Reset Value 0x00000000
Bit 20:
R/W
Timer (TIMER): When TIMER = 1, this bit indicates that the timer has counted down to zero. This interrupt may occur
only once or may occur repeatedly, according to the setting of the TMCONT bit in the TIMER register. Acknowledge
this interrupt by writing a “1” back into this bit position.
Bit 18:
R/W
Command Reset Received (CMDRST): A write request to RESET-START has been received.
Bit 17:
R/W
Fair Gap (FAIRGAP): The serial bus has been idle for a fair-gap time (called subaction gap in the IEEE 1394
specification).
Bit 16:
R/W
Arbitration Reset Gap (ARBGAP): The serial bus has been idle for an arbitration reset gap.
Bit 15:
R/W
Phy Chip Int (PHYINT): The Phy chip has signaled an interrupt through the Phy interface after a bus reset or PHY
reset. This bit becomes active for any of the following reasons (1) PHY has detected a loop on the bus, (2) cable
power has fallen below the minimum voltage, (3) the PHY arbitration state machine has timed-out usually indicative
of a bus loop, (4) a bus cable has been disconnected. Typically, recognition and notification of any of the above
events by the PHY requires between 166 and 500 microseconds; therefore, this bit is not instantaneously set.
Bit 14:
R/W
Phy Register Information Received (PHYRRX): A register has been transferred by the Physical Layer device into the
Link.
Bit 13:
R/W
Phy Reset Started (PHYRST): A Phy-layer reconfiguration has started. This interrupt clears the ID valid bit. (Called
Bus Reset in the IEEE 1394 specification). The Async queues will be flushed during a bus reset.
Bit 10:
R/W
Isochronous Transmitter is Stuck (ITBADFMT): The transmitter has detected invalid data at the transmit-FIFO
interface when the Isochronous Transmit FIFO is selected. Reset the isochronous transmitter to clear.
Bit 9:
R/W
Asynchronous Transmitter is Stuck (ATBADFMT): The transmitter expected start of new async packet in queue, but
found other data (out of sync with user). Reset the asynchronous transmitter to clear.
Bit 8:
R/W
Busy Acknowledge Sent by Receiver (SNT_REJ): The receiver was forced to send a busy acknowledge to a packet
addressed to this node because the receiver response/request FIFO overflowed.
Bit 7:
R/W
Header Error (HDRERR): The receiver detected a header CRC error on an incoming packet that may have been
addressed to this node.
Bit 6:
R/W
Transaction Code Error (TCERR): The transmitter detected an invalid transaction code in the data at the transmit
FIFO interface.
Bit 5:
R/W
Cycle Timed Out (CYTMOUT): ISOCH cycle lasted more than 125
s from Cycle-Start to Fair Gap: Disables cycle
master function
Bit 4:
R/W
Cycle Second incremented (CYSEC): The cycle second field in the cycle-timer register incremented. This occurs
approximately every second when the cycle timer is enabled.
Bit 3:
R/W
Cycle Started (CYSTART): The transmitter has sent or the receiver has received a cycle start packet.
Bit 2:
R/W
Cycle Done (CYDONE): A fair gap has been detected on the bus after the transmission or reception of a cycle start
packet. This indicates that the isochronous cycle is over; Note: Writing a value of ‘0’ to the bit has no effect.
Bit 1:
R/W
Cycle Pending (CYPEND): Cycle pending is asserted when cycle timer offset is set to zero (rolled over or reset) and
stays asserted until the isochronous cycle has ended.
Bit 0:
R/W
Cycle Lost (CYLOST): The cycle timer has rolled over twice without the reception of a cycle start packet. This only
occurs when cycle master is not asserted.
相關(guān)PDF資料 |
PDF描述 |
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| 08008GOB | 125 A, 800 V, SCR, TO-209AC |
| 935268252551 | 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144 |
| 08008GOC | 125 A, 800 V, SCR, TO-209AC |
| 08008GOD | 125 A, 800 V, SCR, TO-208AD |
| 08010GOB | 125 A, 1000 V, SCR, TO-209AC |
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