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參數(shù)資料
| 型號： | 84301 |
| 英文描述： | 84301 4-Port Fast Ethernet Controller manual 3/98 |
| 中文描述： | 84301 4端口快速以太網(wǎng)控制器手冊3 / 98 |
| 文件頁數(shù)： | 59/62頁 |
| 文件大小： | 606K |
| 代理商： | 84301 |
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84301 4-Port
Fast Ethernet Controller
4-59
MD400158/D
Page 3: 1.0 Pin Description
- Description, Register Select Address, ...A4 (206) has an internal ... has been changed to ...A3 (153) and A4 (206)
each has an internal pull down...
Page 5: 1.0 Pin Description (cont.)
- Description, Receive/Transmit Data, Pins 96-101, 107-112 have been added.
- Description, Receive/Transmit Data, ...This is the bidirectional data bus for reads or writes to the chip’s receive
and transmit FIFO’s... has been changed to ...This is the bidirectional data bus for reads from the receive
FIFO or writes to, the transmit FIFO of the chip...
Page 11: Figure 1. Individual Functional Block Diagram
- Reference to RXINTEN has been changed to RXINTEN, reference to TXINTEN has been changed to TXINTEN,
reference to RXRD has been changed to RXRD_TXWR.
Page 14: Section 3.2.2 Transmission Initiation/Deferral has been changed to 3.2.2 Transmission Initiation in Full Duplex
and CSMA/CA Networks and this section 3.2.2 has been replace with new copy.
Page 18: Beginning on page 18 a pagination change has occurred, from pages 18 to the rest of the document.
Page 18: Conditions that cause the RXDC pin to go HIGH
- “Description of How Receive Packets are Discarded”, has been changed to “3.3.5 Receive Discard
Conditions”.
Page 21: 3.5.2 Transmit FIFO Interface
- Paragraph 5, ... one more write after... has been changed to ...one more internal FIFO write after...
Page 22: 3.5.3 Receive FIFO Interface
- Paragraph 6, When the chip is used ... has been added.
- Paragraph 9, ...high going edge of the read... has been changed to ...high going edge of the RXRD_TXWR
of the read...
- Paragraph 10, ...In the case of SPDTAVL being driven low upon the high going edge of the read that meets one
of the above conditions, the SPDTAVL... has been changed to ...When one of the above conditions is met and
SPDTAVL is driven low upon the high going edge of the RXRD_TXWR, the SPDTAVL...
- 3.6.1 Internal Channel Register Addressing Table has been changed to Internal Port Register
Addressing Table.
Page 23: 2.0 Port Register Addressing Table, has been changed to 3.6.1 Internal Port Addressing Table.
Page 24: 2.0 Port Register Addressing Table (continued), has been changed to 3.6.1 Internal Port Addressing Table
(continued).
Page 25: 3.6.3 Transmit Command Register
- Paragraph 2, “Clearing Interrupts” has been changed to “Clearing Interrupts” in section 3.3.5.
- Transmit Command Register Format
- Note ...Please refer to the mode port/select table for details... has been changed to ...Please refer to
"3.6.1 Internal Port Register Addressing Table” for details...
Page 27: Receive Command Register Format
- Note, ...*This register can be used as a write only or a Read/Write register by configuring the address
input accordingly. Please refer to “3.6.1 Internal Port Register Addressing Table” for details... has been added.
Page 30: Full Duplex/Half Duplex Modes Operation with Receive Own Transmit Disable. TABLE A
- Loopback Mode, and Reserved Functional Description have been added to this table.
- Note: There is no internal loopback within the MAC . Loopback is dependent on a PHY connected to the
MAC, has been added.
- Mode F: Full Duplex Mode, ...(pin #108)... has been changed to ...(pin #123, 124, 125, or 127)...
- Mode F, Note: ...Please refer to Mode D for details... has been changed to ...Please refer to Table A
for details...
Page 31: - Mode C: EOF on Data Bit 2 has changed to Mode C: EOF on Data.
- Configuration Register #2, Bit 5 row has changed.
- Note 3. This bit address is shared for two functions, and Note 4. Read will clear this bit to ‘0’, have been added.
Revision History
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