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參數(shù)資料
| 型號： | 84301 |
| 英文描述： | 84301 4-Port Fast Ethernet Controller manual 3/98 |
| 中文描述： | 84301 4端口快速以太網(wǎng)控制器手冊3 / 98 |
| 文件頁數(shù)： | 37/62頁 |
| 文件大小： | 606K |
| 代理商： | 84301 |
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84301 4-Port
Fast Ethernet Controller
4-37
MD400158/D
3.6.11 Full Duplex Status Register
A port’s Full Duplex status can be read from bit 0 of this
register. A read back value of ‘1’ indicates that the port is
in Full Duplex mode which is enabled by either the soft-
ware bit setting (configuration register #1 bit 3 and 5 ) or he
hardware setting (pin # 123, 124, 125 or127).
3.7 COUNTERS
Each 84301 port supports fifteen 32-bit receive/transmit
statistics counters, as described below:
CRC Error Counter
[1]
-
This counter is incremented by 1
any time a frame is received with a proper preamble and
start frame delimiter that has greater than or equal to 64
bytes of data, excluding preamble and ncluding CRC, and
also has a CRC error.
Runt Frame Counter
[1]
-
This counter is incremented by
1 any time a frame is received with a proper preamble and
Start Frame delimiter that has less than 64 bytes of data,
excluding preamble and including CRC.
Oversize Frame Counter
[1]
-
This counter s ncremented
by 1 any time a frame is received with a proper preamble
and start frame delimiter that has greater than 1518 bytes
of data excluding preamble bytes and including CRC.
Alignment Error Counter
[1]
-
This counter s ncremented
by 1 any time a frame is received with a proper preamble
and start frame delimiter that has greater than 64 bytes of
data, excluding preamble and ncluding CRC, and also has
a CRC error and a non-integral number of octets of data.
Transmit Collisions Single Retry
- This counter s ncre-
mented by 1 any time a frame requires 1 and only 1
retransmission due to a collision before it is successfully
transmitted. Late transmit collision occurrences will never
cause this counter to be incremented. This counter will
never be incremented if the port is in full-duplex mode
since in this mode a port’s COLL pin should never be
driven HIGH.
Transmit Collisions Multiple Retries
- This counter is
incremented by 1 any time a frame requires greater than
1 but less than 16 retransmission attempts before it is
successfully transmitted. Late transmit collision occur-
rences will never cause this counter to be incremented.
This counter will never be incremented if the port is in full-
duplex mode since in this mode a port’s COLL pin should
never be driven HIGH.
Transmit Collision Sixteen Retries
- This counter is
incremented by 1 any time a frame fails to be transmitted
due to 16 collision occurrences. If the 16th collision s also
a ate collision hen both his counter and he Late Collision
Counter will be incremented. This counter will never be
incremented if the port is in full-duplex mode since in this
mode a port’s COLL pin should never be driven HIGH.
Receive Collisions -
This counter is incremented by 1
any time the chip is not transmitting, the TXEN output is
LOW, and the COLL pin goes HIGH for greater than 2
receive clock cycles 6.4
μ
s after TXEN has gone LOW if
this is in 10 MBit/sec serial mode.
Transmit FIFO Underruns
- This counter is incremented
by 1 any time a Transmit FIFO Underrun error occurs. A
transmit FIFO Underrun Error occurs any time the trans-
mitter empties the transmit FIFO before seeing an end of
frame indication in the FIFO.
Late Collisions
- This counter is incremented by 1 any
time a collision occurs greater than 64 byte times after
TXEN has gone high during the transmission of a frame.
This counter will never be incremented if the port is in full-
duplex mode since in this mode a port’s COLL pin should
never be driven HIGH.
Loss of Carrier
- This counter is incremented by 1 any
time when during the transmission of a frame as ndicated
by TXEN being HIGH, carrier sense never goes HIGH or
carrier goes from HIGH to a LOW.
Transmit Deferred
- This counter s ncremented by 1 any
time that the transmit FIFO has data and the transmitter s
ready to start transmission but the transmitter has to defer
transmission due to carrier sense being HIGH. This
counter will never be incremented if the port is in full-
duplex mode.
Receive FIFO Overflow
- This counter s ncremented by
1 any ime an ncoming receive packet causes he receiver
to attempt to write to a full Receive FIFO.
Transmit Frames
- This counter is incremented by 1 any
time a frame is transmitted successfully by the port.
Transmit Octets
- This counter s ncremented by he otal
number of octets of data excluding preamble but ncluding
CRC of a transmit frame if that frame was successfully
transmitted.
3.7.1 Accessing the Counters
The counters will be accessed through the 8-bit Register
Interface Bus. Write operations to the counters will have
no effect. Read operations will be conducted through
multiple 8-bit accesses. Accesses o register space which
are interleaved with those to read the counters shall not
disturb he counter accesses. The contents of all counters
Note1:
Whether these counters are 16-bit or 32-bit depends on the value of bit 2 of Configuration Register #3.
(See Section 3.6.7)
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