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參數(shù)資料
| 型號： | 84301 |
| 英文描述： | 84301 4-Port Fast Ethernet Controller manual 3/98 |
| 中文描述： | 84301 4端口快速以太網(wǎng)控制器手冊3 / 98 |
| 文件頁數(shù)： | 20/62頁 |
| 文件大小： | 606K |
| 代理商： | 84301 |
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84301 4-Port
Fast Ethernet Controller
4-20
MD400158/D
receive discard, the FIFO will be flushed only up to the ast
completely received packet. To prevent a receive packet
from being discarded due to an error condition, you can
selectively enable the reception of errored packets as
described n the section describing bit settings on configu-
ration register #2.
Conditions that Cause the RXDC Pin to go HIGH
As packets are discarded due to the receive packet
error conditions given in section “3.3.5 Receive
Discard Conditions”, the corresponding port’s RXDC
pin may or may not assert. If a receive packet’s status
has been written to the receive FIFO and the packet’s
status has not yet been read from the FIFO, discards
caused by following packets with errors are handled
within the chip and the RXDC pin will not go HIGH. If
all status double words for all packets written to the
FIFO have been read out then the RXDC pin will go
HIGH under the following condition:
1. Enough of a receive packet has been written to
the FIFO o cause RXRDY o go HIGH before he
packet is discarded due to an error condition.
2. If there are no status double words n the receive
FIFO and if RXRDY goes HIGH just before a
discard condition occurs, RXRDY may go LOW
again before any FIFO reads have occurred.
This is due to thereceive discard clearing the
FIFO of any receive bytes already written to the
FIFO. In this case, RXRDY is guaranteed to
remain HIGH for at least one RXRD_TXWR
clock cycle.
Detecting and Clearing a Receive Discard
Condition
To enable the output driver for the RXDC pins,
the RXINTEN input must be driven low. Once a
discard condition is detected, the receive discard can
be cleared by driving he RXINTEN nput ow and hen
pulsing the CLRRXERR input high for a minimum of
one RXRD_TXWR clock cycle. The RXINTEN input
must not change state for the duration of the time that
the CLRRXERR input is high.
Clearing Interrupts
Within one port, both receive and transmit interrupts
are combined nto a single nterrupt signal which then
goes to the INT output pin. The interrupt signal in the
chip s actually he result of he receive/transmit status
register outputs and the receive/transmit command
register interrupt enable bits that are set. To clear an
interrupt, the status that caused the nterrupt needs to
be cleared. This can be accomplished by reading the
transmit status register and/or the receive status
register.
3.4 SYSTEM INTERFACE
The chip system nterface consists of one receive/transmit
32-bit bidirectional data bus, one 8-bit bidirectional com-
mand/status data bus, and each busses respective control
signals. Receive FIFO data is read and Transmit FIFO
data is written over the RXTXDATA[31:0] bus, and Com-
mand/Status data is written or read over the bidirectional
CDST[7:0] data bus.
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