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參數(shù)資料
| 型號： | 84301 |
| 英文描述： | 84301 4-Port Fast Ethernet Controller manual 3/98 |
| 中文描述： | 84301 4端口快速以太網(wǎng)控制器手冊3 / 98 |
| 文件頁數(shù)： | 23/62頁 |
| 文件大?。?/td> | 606K |
| 代理商： | 84301 |
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84301 4-Port
Fast Ethernet Controller
4-23
MD400158/D
Depending on the way RXRDEN is used, two different
modes are possible, when the chip is used in the non-
bidirectional byte enable mode.
On burst reads (RXRDEN being asserted or multiple clock
cycles), if the first read is not a double word read, the
second read will always increment the FIFO pointer irre-
spective of whether all he byte enables are enabled or not.
In this mode, 16 bit reads are possible by muxing the LSB
and the MSB of the data bus. 8 bit reads are not possible.
On single reads (RXRDEN being asserted for only one
clock cycle), the FIFO pointer will get incremented only on
a double word read. In this mode, the different bytes of the
data bus can be muxed to perform multiple 8 bit or 16 bit
reads. But, all the reads of the bytes belonging to one row
should be erminated with a double word read o ncrement
the FIFO pointer.
When the chip is used in the bidirectional byte enable
mode, all reads will have all four byte enable bits asserted
except for the last data double word which could have all
or partial byte enable bits asserted depending on the
received data byte count.
When he chip s being read, he RXRDY output will remain
high until the high going edge of the read that results n one
of the following conditions:
1. The FIFO no longer has enough data to meet the
threshold setting.
2. A packet’s status double word with its associated
HIGH end of frame value is read out.
In the case of RXRDY being driven LOW upon condition
two given above, it will remain LOW for 8 RXRD_TXWR
clock cycles and then goes back HIGH if one of the
conditions for RXRDY being HIGH is met.
During reads from the FIFO, the SPDTAVL output will
remain high until the high going edge of the RXRD_TXWR
of the read that causes one of the following conditions to
occur:
1. The read that empties the FIFO completely.
2. The read that reads a packets status double word
from the FIFO.
When one of the above conditions s met and SPDTAVL s
driven ow upon the high going edge of the RXRD_TXWR,
the SPDTAVL output will remain low for a period of 8
RXRD_TXWR clock cycles. For the time that SPDTAVL
remains ow, urther reads are blocked within he chip even
if external reads continue. This allows overreading the
receive FIFO by a few cycles without, internal to the chip,
reading an empty FIFO or reading new packet data before
the present packet is processed. It is up to the processor
doing the FIFO reads to determine on which read cycle the
SPDTAVL went low and thereby which read cycles are
over reads containing invalid data.
3.5.4 Special Conditions on the RXRD_TXWR input
This nput s required to be tied to a continuous clock signal
whose maximum clock frequency can be 33Mhz. The
number of read or write cycles occurring to the chip is
controlled through the TXWREN and RXRDEN inputs. All
transitions of the TXRDY, RXRDY, RXTXEOF, SPDTAVL,
RXDC, RXTXDATA[31:0], and TXRET outputs are syn-
chronized internally to the RXRD_TXWR clock and are
clocked to the output drivers on the highgoing edge of the
clock.
3.6 REGISTER INTERFACE
3.6.1 Internal Port Register Addressing Table
Writing of Command, Configuration, and Station Address
registers and reading of status registers is controlled by
the ENREGIO, RD, WR, REGPS[1:0], and A[4:0] signals.
The ENREGIO signal is used as a general register inter-
face enable and must be active low before any register
operations can occur. The REGPS signals are used to
select which port’s registers are to be accessed. The
A[4:0] are used to address which register within a port is
being accessed. nitiation of a register read s controlled by
the RD signal and initiation of a register write is controlled
by the WR signal. A port’s registers may be accessed at
any time. However, it is recommended that writing to the
command register, be done only during interframe gaps.
With the exception of the two Match Mode bits in the
Receive Command Register, all bits in both command
registers are interrupt enable bits. Changing the interrupt
enable bits during frame transmission does not affect the
frame integrity. Asynchronous error events, however,
e.g., overflow, underflow, etc., may cause chip operation
to vary, f their corresponding enable bits are being altered
at the same time.
Reading the status registers may also occur at any time
during transmission or reception.
Status Registers and all management counters are read
only registers. The Rx and Tx Command Registers are
write only or read/write registers based on the address
inputs. Please refer to the mode/port select table for
details. All other registers are writable and readable.
Access to these registers s via the CPU nterface: Control
signals ENREGIO, RD, WR, REGPS [1:0] A[4:0], and the
Command/Status Data Bus CdSt [7:0].
3.6.2 Station Address Register
The Station Address Register is 6 bytes in length. The
contents may be written n any order, with bit “0” of byte “0”
corresponding to the first bit received in the data stream,
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