參數(shù)資料
型號(hào)： 84301
英文描述： 84301 4-Port Fast Ethernet Controller manual 3/98
中文描述： 84301 4端口快速以太網(wǎng)控制器手冊(cè)3 / 98
文件頁(yè)數(shù)： 14/62頁(yè)
文件大?。?/td> 606K
代理商： 84301
84301 4-Port
Fast Ethernet Controller
4-14
MD400158/D
3.0 Functional Description
On an Ethernet communication network, information is
transmitted and received in packets or frames. An Eth-
ernet frame consists of a preamble, two address fields, a
byte-count field, a data field and a frame check sequence
(FCS). Each field has a specific format which s described
in detail below. An Ethernet frame has a minimum length
of 64 bytes and a maximum ength of 1518 bytes exclusive
of he preamble. The Ethernet rame ormat s shown n he
figure below.
3.1 FRAME FORMAT
2.0 Introduction
The 84301 is a 4-Port Ethernet Media Access Controller
(MAC) with a rich set of operating modes and features. It
is manufactured as a single-chip VLSI device to simplify
and enhance the development of multi-port Ethernet em-
bedded systems such as bridges, switches, and routers.
Two input/output paths are provided for interfacing to
physical layer devices. In IEEE-standard MII mode, the
84301 provides an industry standard interface supporting
both 10Mbit/sec and 100Mbit/sec data rates. This inter-
face will directly connect with physical layer devices such
as SEEQ’s 80C240 100Base-T4 PHY without additional
glue logic. In Serial mode, the chip supports the standard
Ethernet CSMA/CD protocol via a serial interface for
transmit and receive data. All ports, n all nterface modes,
support both Half and Full Duplex operation.
Each port of the 84301 is feature compatible with SEEQ’s
80C300 Ethernet Media Access Controller. These fea-
tures include: 64 bit Multicast filter, Transmit no CRC,
Transmit no Preamble, Transmit Packet Autopadding,
Receive CRC, Receive Own Transmit Disable, Receive
Group Address Mode, Fast Receive Discard Mode, and
Full Duplex Mode. Additionally, each port supports: pro-
grammable defer time between transmit packets, append-
ing value of FCS on a packet-by-packet basis, and pin-
controllable per-port receive packet abort.
A high-bandwidth universal system interface is provided
which is compatible with many microprocessor or system
busses, easing the integration of the 84301 into many
system architectures. Its 32-bit data path width s provided
to provide the bandwidth necessary to maintain full duplex
wire speed communications simultaneously through all
four ports. Each port s provided with dual 128 byte FIFOs
to ease bus multiplexing and interfacing to different clock
domains.
NOTE:
Field length bytes, in parentheses.
FIRST BYTE
LAST BYTE
DESTINATION
ADDRESS
(6 BYTES)
SOURCE
ADDRESS
(6 BYTES)
BYTE COUNT
(2 BYTES)
DATA
(46 – 1500
BYTES)
A7
A15
A23
A31
A39
A47
B7
B15
B23
B31
B39
B47
T7
T15
D7
A0
A8
A16
A24
A32
A40
B0
B8
B16
B24
B32
B40
T0
T8
D0
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Typical Frame Buffer Format for
Byte-Organized Memory
PREAMBLE
(8)
DESTINATION
ADDRESS
(6)
SOURCE
ADDRESS
(6)
BYTE
COUNT
(2)
DATA
(46-1500)
FCS
(4)
ETHERNET FRAME
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