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參數(shù)資料
| 型號： | 84301 |
| 英文描述： | 84301 4-Port Fast Ethernet Controller manual 3/98 |
| 中文描述： | 84301 4端口快速以太網(wǎng)控制器手冊3 / 98 |
| 文件頁數(shù)： | 3/62頁 |
| 文件大?。?/td> | 606K |
| 代理商： | 84301 |
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84301 4-Port
Fast Ethernet Controller
4-3
MD400158/D
Pin
Pin Name
I/O
Description
Chip Registers’ Interface
22
ENREGIO
I
Enable Register I/O Operations
This active low input enables the chip for register operations. This input must be
low before any port’s registers can be written or read.
4
W R
I
Write Strobe
For a selected port within the chip, this input acts as a write strobe for one of the port’s
registers. The port is selected through the REGPS[1:0] inputs and the register is
addressed through the A[4:0] address inputs. The data being written appears on the
CDST[7:0] data lines and must be set up relative to the rising edge of the write strobe.
This input is active low.
5
R D
I
Read Strobe
For a selected port within the chip, this input acts as a read strobe for one of the port’s
registers. The port is selected through the REGPS[1:0] inputs and the register is
addressed through the A[4:0] address inputs. When the read strobe is active low,
the output drivers for CDST[7:0] data bus are enabled. Valid register data appears
on the data bus a specified time before the rising edge of the read strobe.
21, 20
REGPS[1:0]
I
Register Port Select Inputs
These inputs are used to select which port’s registers are read or written by asserting
the RD or WR read or write strobe inputs. Binary values of 00 through 11 select
channels 1 through 4 respectively with REGPS1 being the MSB of the binary value.
REGPS1
REGPS0
Selected
Port
Port 1
Port 2
Port 3
Port 4
0
0
1
1
0
1
0
1
206, 153,
6, 7, 8
A[4:0]
I
Register Select Address
These inputs are the address lines used to select which register within a port is being
read or written. A3 (153) and A4 (206) each has an internal pull down to ensure
backward compatibility with the 84C300A.
9-12
15-18
CDST[7:0]
I/O
Register Data
These bidirectional lines carry register data to or from the internal registers of each
port in the chip. These lines are nominally high impedance until their output drivers
are enabled by the RD and ENREGIO input pins being driven low.
47, 61,
68, 77
INT_[1:4]
O
Interrupts
These outputs are driven by a variety of Transmit and Receive interrupt conditions
of a particular port. If remains HIGH until the corresponding port’s Status Register
containing the reason for the interrupt is read.
49
RESET
I
Hardware Reset
This input is an active low asynchronous chip reset. After reset, all registers except
the Hash and Station Address registers are reset to zero, all FIFOs are cleared,
all counters are reset to zero.
1.0 Pin Description
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