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參數(shù)資料
| 型號： | 84301 |
| 英文描述： | 84301 4-Port Fast Ethernet Controller manual 3/98 |
| 中文描述： | 84301 4端口快速以太網(wǎng)控制器手冊3 / 98 |
| 文件頁數(shù)： | 21/62頁 |
| 文件大小： | 606K |
| 代理商： | 84301 |
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84301 4-Port
Fast Ethernet Controller
4-21
MD400158/D
3.5 FIFO INTERFACE
3.5.1 Little Endian and Big Endian Format
The FIFO nterface control ncludes the BUSMODE bit 7 n
configuration register #2, which sets the 84301 FIFO
interface to Big Endian or Little Endian byte transmit/
receive data order. In Big Endian mode, data written to the
transmit FIFO is transmitted most significant byte of the
RXTXDATA bus first and least significant byte of the
RXTXDATA bus last. In Little Endian mode, the least
significant byte of each double word s transmitted first and
the most significant byte of each double word is transmit-
ted ast. On the receive side, f Big Endian mode s n effect
then the first data bytes received are assumed to be the
most significant bytes of the double word and appear on
the most significant portion of the RXTXDATA bus for
receive FIFO reads. The receiver reverses this order f the
chip is in Little Endian mode. The value of the BUSMODE
bit has no effect on the operation of the 84301 register
interface. It is important to note that the operation of the
byte enables remain the same for both modes.
3.5.2 Transmit FIFO Interface
To determine f the transmit FIFO for any of the chips ports
has reached its threshold number of double words of
space available, all our TXRDY outputs can be enabled by
driving the TXINTEN input low. The TXRDY output for a
port will be high if there is enough space available in the
port's transmit FIFO to meet or exceed the programmed
threshold value.
Once one of the TXRDY outputs is determined to be high,
that port’s Transmit FIFO can be written. To write to a
port’s Transmit FIFO, the TXWREN and TXINTEN inputs
must be asserted ow and at east one of the RXTXBE byte
enables must be ow for each write cycle. The value of the
RXTXPS nputs determines which port s being written. All
of the above inputs are clocked into the chip on the high
going edge of the RXRD_TXWR clock input which also
acts as the FIFO write strobe. Because of this pipe lining
the actual FIFO write will occur one RXRD_TXWR cycle
after the assertion of the Transmit FIFO interface control
Bit Serialization/Deserialization for Big Endian Format
Bit Serialization/Deserialization for Little Endian Format
PREAMBLE
1ST BYTE
6TH BYTE
A0 . . . A7
A8 . . . A15
SOURCE ADDRESS . . .
DESTINATION ADDRESS
BITS WITHIN A DOUBLE WORD TRANSMITTED/RECEIVED BIT NO.“0” FIRST THROUGH BIT NO. “31” LAST.
A40 . . . A47
A32 . . . A39
A24 . . . A31
A16 . . . A23
5TH BYTE
4TH BYTE
3RD BYTE
2ND BYTE
RXTXDATA0
RXTXDATA7
RXTXDATA24
RXTXDATA31
RXTXDATA0
RXTXDATA7
PREAMBLE
1ST BYTE
6TH BYTE
A0 . . . A7
A8 . . . A15
SOURCE ADDRESS . . .
DESTINATION ADDRESS
A40 . . . A47
A32 . . . A39
A24 . . . A31
A16 . . . A23
5TH BYTE
4TH BYTE
3RD BYTE
2ND BYTE
RXTXDATA24
RXTXDATA31
RXTXDATA0
RXTXDATA7
RXTXDATA24
RXTXDATA31
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