參數(shù)資料
型號(hào)： 5962F0721401VZC
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： ADC
英文描述： 2-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP128
封裝： CERAMIC, MS-026BFB, QFP-128
文件頁(yè)數(shù)： 7/44頁(yè)
文件大小： 1491K
代理商： 5962F0721401VZC
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M32000D4BFP-80
15
The user I/O area is 8 MB from address H'FF00 0000 to address
H'FF7F FFFF. When this space is accessed, the control signals to
access external devices are output. The system area is 4 MB from
address H'FF80 0000 to address H'FFBF FFFF. This area is reserved
for development tools such as in-circuit emulators or debug moni-
tors. The user cannot use this area.
The internal I/O area is 4 MB from address H'FFC0 0000 to address
H'FFFF FFFF. The memory controller and programmable I/O port
registers are allocated in this area.
The internal DRAM (2 MB) is allocated from address H'0000 0000 to
address H'001F FFFF. The EIT vector entry (other than the reset
interrupt) is allocated in the address H'0000 0000 to address H'0000
008F of this area.
The internal DRAM is connected to the M32R CPU via a 4 KB cache
memory with a 128-bit bus. When the M32000D4BFP-80 is in the
hold state, the internal DRAM can be accessed from an external bus
master by inputting control signals.
The external area consists of 14 MB from address H'0020 0000 to
address H'00FF FFFF. When this space is accessed, the control sig-
nals to access external devices are output. The bottom 16 bytes in
this area (H'00FF FFF0 to H'00FF FFFF) are the reset interrupt EIT
vector entry.
Fig. 10 Internal I/O space memory map
H'FFC0 0000
H'FFFF FFE0
H'FFFF FFE4
H'FFFF FFE8
H'FFFF FFF8
H'FFFF FFFC
logical address
031
+3 address
(reserved)
+2 address
+1 address
+0 address
PPCR1
PPDR0
memory controller
PPDR1
(reserved)
MPMR
MCCR
PPCR0
H'FFFF FFEC
MLCR: lock control register
MPMR: power management control register
MCCR: cache control register
programmable I/O port
PPCR0: programmable I/O port direction control register 0
PPCR1: programmable I/O port direction control register 1
PPDR0: programmable port data register 0
PPDR1: programmable port data register 1
MLCR
H'FFFF FFF4
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