參數(shù)資料
型號(hào)： 5962F0721401VZC
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類(lèi)： ADC
英文描述： 2-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP128
封裝： CERAMIC, MS-026BFB, QFP-128
文件頁(yè)數(shù)： 36/44頁(yè)
文件大?。?/td> 1491K
代理商： 5962F0721401VZC
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M32000D4BFP-80
41
Fig. 41 Bus arbitration timing
CLKIN
HREQ
HACK
A8 to A30, SID, ST,
BS, BCH, BCL,
R/W, BURST
(output)
(input)
(output)
*1 The HREQ signal can be input asynchronously.
*2 All switching characteristics and timing requirements based on the falling edge of CLKIN are calculated according to
the internal CLKIN (duty ratio is 50%) . When designing external peripheral circuits, the correction for the duty cycle of
the actual CLKIN is necessary.
minimum value of td(CLKIN-HACKHX) = (value in table) – (correction value) = 0 – (50 x 5/100) = –2.5 [ns]
maximum value of td(CLKIN-HACKL) = (value in table) + (correction value) = 8 + (50 x 5/100) = 10.5 [ns]
[example]
HACK signal transition ("H" –> "L") when inputting 20 MHz clock whose duty ratio is 45 - 55% (± 5%) to CLKIN:
0.5VCC
td(CLKIN-HACKL)
td(CLKIN-HACKHX)
td(CLKIN-HACKH)
td(CLKIN-HACKLX)
td(CLKIN-AZX)
td(CLKIN-AZ)
tsu(HREQ-CLKIN)
41
42
43
44
45
46
47
*1
th(CLKIN-HREQ)
40
*2
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