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參數(shù)資料
| 型號： | 5962F0721401VZC |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 2-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP128 |
| 封裝： | CERAMIC, MS-026BFB, QFP-128 |
| 文件頁數(shù)： | 20/44頁 |
| 文件大?。?/td> | 1491K |
| 代理商： | 5962F0721401VZC |
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SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M32000D4BFP-80
27
In standby mode, all clock supply stops and only the contents of the
internal DRAM are retained. The power requirement is only that which
the internal DRAM needs for refreshing itself. When set to standby
mode, the M32000D4BFP-80 waits for the current bus operation to
be completed. It then purges the cache memory and switches the
internal DRAM to self-refresh mode. After that, the PLL and all clock
_____
supplies stop and the STBY signal goes to an "L" level to indicate the
_____
completion of the switch to standby mode. Input an "L" level to WKUP
___
or RST to return from standby mode to normal operation mode. The
contents of the internal DRAM are retained upon return using the
_____
WKUP signal.
In CPU sleep mode, clock supply to the M32R CPU stops. In this
mode, the internal DRAM, cache memory, memory controller and
external bus interface continue to operate and the internal DRAM
___ ___
can be accessed from the external bus. Input an "L" level to INT, SBI
___
or RST to return to normal operation mode from CPU sleep mode.
The contents of the cache memory, internal DRAM, general-purpose
registers and programmable I/O control register are retained upon
___
return using the INT or SBI signals.
Power management function
The M32000D4BFP-80 has the following two low-power consump-
tion modes.
standby mode
CPU sleep mode
power management (MPMR) < address: H'FFFF FFFB>
D24
D25
D26
D27
D28
D29
D31
PM1
PM0
D30
<at reset: H'00>
D
bit name
function
R
W
24 - 29
Not assigned.
0
30, 31
PM0, PM1
(low power
consumption
mode)
00: normal
operation
mode
01: (reserved)
10: CPU sleep
mode
11: standby mode
Fig. 28 Power management control register
standby mode
reset
normal
operation mode
CPU sleep
mode
set to CPU sleep mode
(H'02 is written to
MPMR register)
set to standby mode
(H'03 is written to
MPMR register)
INT, SBI, RST
input
WKUP, RST
input
Fig. 29 State transition for low power consumption mode
R = 0 ... "0" when reading
R =
... read enabled
W =
... write enabled
W =
: write disabled
!
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