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參數(shù)資料
| 型號： | 5962F0721401VZC |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 2-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP128 |
| 封裝： | CERAMIC, MS-026BFB, QFP-128 |
| 文件頁數(shù)： | 38/44頁 |
| 文件大?。?/td> | 1491K |
| 代理商： | 5962F0721401VZC |
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SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M32000D4BFP-80
43
Fig. 43 Interrupt input timing
Fig. 44 Standby timing
PX
tw(PORTINL)
tw(PORTINH)
69
70
[for input]
PX
tw(PORTOUTL)
tw(PORTOUTH)
71
72
[for output]
Fig. 45 I/O port timing
INT
SBI
(input)
tw(INT)
tw(SBI) *1
63
64
*1
*1 The INT and SBI signals can be input asynchronously.
When returning from CPU sleep mode, the same timing applies.
This timing value is "a value necessary for sampling the input to pins", however, not "a value
that guarantees the interrupt acceptance".
The interrupt request is a level-sensed input , and should be kept "L" until it is accepted.
*2 The STBY goes to an "L" level when switched to the standby mode.
*3 When returning from standby mode, the STBY signal goes to an "H" level 1 CLKIN after
sampling that WKUP has returned from "L" to "H", or 3 CLKINs after sampling that RST = "L".
td(CLKIN-STBYL)
STBY
(output)
66
CLKIN
(input)
td(CLKIN-STBYH)
68
*1 *2
*1 *3
degree phase of CLKIN.
td(CLKIN-STBYHX)
65
td(CLKIN-STBYLX)
67
internal clock
(80 MHz)
*1 The STBY signal is synchronized with the internal clock therefore, its timing changes at 0, 90, 180 and 270
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