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參數(shù)資料
| 型號： | 5962F0721401VZC |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 2-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP128 |
| 封裝： | CERAMIC, MS-026BFB, QFP-128 |
| 文件頁數(shù)： | 13/44頁 |
| 文件大小： | 1491K |
| 代理商： | 5962F0721401VZC |
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SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M32000D4BFP-80
20
__
Internal DRAM access control (CS)
__
The internal DRAM can be accessed when CS is driven to an "L"
____
level after the M32000D4BFP-80 enters the hold state (HACK = "L").
To access the internal DRAM from external, the following signals
from the system bus side should be controlled.
A8 to A30
Input internal DRAM addresses to be read or written.
___
BCH, BCL
Specify the byte position of data to be written into the internal
___
DRAM. BCH corresponds to the MSB side (D0 to D7), and BCL
corresponds to the LSB side (D8 to D15).
__
R/W
___
Specify read or write operation. When reading, R/W = "H". When
__
writing, R/W = "L".
D0 to D15
16-bit data I/O bus.
_____
DC
This signal notifies to an external bus master that the internal
DRAM access is complete. When access is complete, an "L"
_____
level is output to DC.
Read and write operations of the M32000D4BFP-80 are carried out
___
_______
_____
using the address bus, data bus, and the R/W, BCH, BCL and DC
___
signals. When reading, the R/W signal goes to an "H" level, and the
_______
BCH and BCL signals go to an "L" level. The CPU reads the data in
the valid byte positions. When writing, an "L" level is output from R/
___
_______
W, and BCH and BCL are output according to the valid byte posi-
tions, so as to specify the byte positions for writing into an external
device.
pin name
pin condition or operation
A8 - A30, SID,
high-impedance
____
BCH, BCL
__
___
______
ST, R/W, BS, BURST
D0 - D15
output when internal DRAM is read
__
by an external bus master (CS = "L",
__
R/W = "H"), otherwise high-impedance
__
DC
output when internal DRAM is
accessed by an external bus master
__
(CS = "L"), otherwise high-impedance
_____
HACK
output "L"
other pins
normal operation
Table 1 Pin condition in hold state
Fig. 16 Read/write timing (two no-wait accesses)
idle
read
"H"
CLKIN
BS
A8 - A30
SID, ST
BCH, BCL
BURST
D0 - D15
DC
R/W
idle
read
idle
write
idle
write
CLKIN
BS
A8 - A30
SID, ST
BCH, BCL
BURST
D0 - D15
DC
R/W
"H"
"Hi-Z"
Note: "Hi-Z" means high-impedance, and
indicates sampling timing.
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