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參數(shù)資料
| 型號： | 5962F0721401VZC |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 2-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP128 |
| 封裝： | CERAMIC, MS-026BFB, QFP-128 |
| 文件頁數(shù)： | 21/44頁 |
| 文件大小： | 1491K |
| 代理商： | 5962F0721401VZC |
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SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M32000D4BFP-80
28
internal resources
state
DRAM
undefined
cache memory
invalid
(purged all)
general purpose
undefined
registers
(R0 - R15)
control registers PSW (CR0)
B'0000 0000 0000 0000 ??00 000? 0000 0000
(BSM, BIE, and BC are undefined)
CBR (CR1)
H'0000 0000
SPI (CR2)
undefined
SPU (CR3)
undefined
BPC (CR6)
undefined
PC
master mode:
execute from address H'7FFF FFF0
slave mode:
wait for interrupt input at address
H'7FFF FFF0
execute from address H'0000 0010
___
by inputting SBI signal
execute from address H'0000 0080
___
by inputting INT signal
ACC
(accumulator)
undefined
I/O registers
PPCR0, PPCR1 H'00 (input)
PPDR0, PPDR1 B'0000 000? (depends on input
pin state)
MLCR
_____
H'00 (HREQ exclusive lock mode)
MPMR
H'00 (normal operation)
MCCR
H'01 (cache-off mode)
Programmable I/O port
The M32000D4BFP-80 has two programmable I/O ports (PP0, PP1).
Each port can be set as input or output.
Reset
____
When an "L" level is input to RST, the M32000D4BFP-80 switches to
the reset state. The reset state is released when an "H" level is input
____
to RST, and the program is executed from the EIT vector entry of the
reset interrupt. All internal resources including the internal PLL (4x
clock generator) are initialized. In order to stabilize PLL oscillation,
____
the "L" input to RST should last a minimum of 2 ms after the clock
input to CLKIN stabilizes and VCC stabilizes to the specified voltage
level.
<at reset: H'00>
D
bit name
function
R
W
24 - 30
Not assigned.
0
31
PP0C, PP1C
0: input port
(port I/O direction)
1: output port
programmable I/O port direction control register 1 (PPCR1)
< address: H'FFFF FFE7>
D24
D25
D26
D27
D28
D29
D30
D31
PP1C
programmable I/O port direction control register 0 (PPCR0)
< address: H'FFFF FFE3>
D24
D25
D26
D27
D28
D29
D30
D31
PP0C
Fig. 30 Programmable I/O port direction control register
programmable I/O port data register 0 (PPDR0)
< address: H'FFFF FFEB>
<at reset: B'0000 000?>
D
bit name
function
R
W
24 - 30
Not assigned.
0
31
PP0D, PP1D
0: data = "0"
(port data)
1: data = "1"
D24
D25
D26
D27
D28
D29
D30
D31
PP1D
programmable I/O port data register 1 (PPDR1)
< address: H'FFFF FFEF>
D24
D25
D26
D27
D28
D29
D30
D31
PP0D
Fig. 31 Programmable I/O port data register
Table 2 Internal state after reset
R = 0 ... "0" when reading
R =
... read enabled
W =
... write enabled
W =
: write disabled
R = 0 ... "0" when reading
R =
... read enabled
W =
... write enabled
W =
: write disabled
!
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