參數(shù)資料
型號(hào)： 5962-0924001VXC
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP100
封裝： HERMETIC SEALED, CERAMIC, QFP-100
文件頁(yè)數(shù)： 9/46頁(yè)
文件大?。?/td> 1109K
代理商： 5962-0924001VXC
InstructionCycle
DataTransferCycle(s)
SDENB
SCLK
SDIO
SDENB
SCLK
SDIO
r/w
N1
N0
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
t (SDENB)
S
tSCLK
t (SDIO)
S
t (SDIO)
h
tSCLKH
tSCLKL
SDENB
SCLK
SDIO
SDO
SDENB
SCLK
SDIO
SDO
InstructionCycle
DataTransferCycle(s)
r/w
N1
N0
-
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
D7
D6
D5
D4
D3
D2
D1
D0
0
3pinConfigurationOutput
4pinConfigurationOutput
Datan
Datan-1
t (Data)
d
SLAS669B
– SEPTEMBER 2010 – REVISED MAY 2011
Figure 6. Serial Interface Write Timing Diagram
Figure 7 shows the serial interface timing diagram for a ADS5400 read operation. SCLK is the serial interface
clock input to ADS5400. Serial data enable SDENB is an active low input to ADS5400. SDIO is serial data in
during the instruction cycle. In 3 pin configuration, SDIO is data out from ADS5400 during the data transfer
cycle(s), while SDO is in a high-impedance state. In 4 pin configuration, SDO is data out from ADS5400 during
the data transfer cycle(s). At the end of the data transfer, SDO will output low on the final falling edge of SCLK
until the rising edge of SDENB when it will 3-state.
Figure 7. Serial Interface Read Timing Diagram
Copyright
2010–2011, Texas Instruments Incorporated
17
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