參數(shù)資料
型號(hào): 5962-0924001VXC
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP100
封裝: HERMETIC SEALED, CERAMIC, QFP-100
文件頁數(shù): 8/46頁
文件大小: 1109K
代理商: 5962-0924001VXC
SLAS669B
– SEPTEMBER 2010 – REVISED MAY 2011
SERIAL INTERFACE
The serial port of the ADS5400 is a flexible serial interface which communicates with industry standard
microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the
operating modes of ADS5400. It is compatible with most synchronous transfer formats and can be configured as
a 3 or 4 pin interface in register 0x01h. In both configurations, SCLK is the serial interface input clock and
SDENB is serial interface enable. For 3 pin configuration, SDIO is a bidirectional pin for both data in and data
out. For 4 pin configuration, SDIO is data in only and SDO is data out only.
Each read/write operation is framed by signal SDENB (Serial Data Enable Bar) asserted low for 2 to 5 bytes,
depending on the data length to be transferred (1
–4 bytes). The first frame byte is the instruction cycle which
identifies the following data transfer cycle as read or write, how many bytes to transfer, and what address to
transfer the data. Table 3 indicates the function of each bit in the instruction cycle and is followed by a detailed
description of each bit. Frame bytes 2 to 5 comprise the data transfer cycle.
Table 3. Instruction Byte of the Serial Interface
MSB
LSB
Bit
7
6
5
4
3
2
1
0
Description
R/W
N1
N0
A4
A3
A2
A1
A0
R/W
Identifies the following data transfer cycle as a read or write operation. A high indicates a read
operation from ADS5400 and a low indicates a write operation to the ADS5400.
[N1:N0]
Identifies the number of data bytes to be transferred per Table 4 below. Data is transferred MSB
first.
Table 4. Number of Transferred Bytes Within One
Communication Frame
N1
N0
Description
0
Transfer 1 Byte
0
1
Transfer 2 Bytes
1
0
Transfer 3 Bytes
1
Transfer 4 Bytes
[A4:A0]
Identifies the address of the register to be accessed during the read or write operation. For
multi-byte transfers, this address is the starting address. Note that the address is written to the
ADS5400 MSB first and counts down for each byte.
Figure 6 shows the serial interface timing diagram for a ADS5400 write operation. SCLK is the serial interface
clock input to ADS5400. Serial data enable SDENB is an active low input to ADS5400. SDIO is serial data in.
Input data to ADS5400 is clocked on the rising edges of SCLK.
16
Copyright
2010–2011, Texas Instruments Incorporated
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