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| 型號(hào)： | 5962-0924001VXC |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP100 |
| 封裝： | HERMETIC SEALED, CERAMIC, QFP-100 |
| 文件頁數(shù)： | 30/46頁 |
| 文件大?。?/td> | 1109K |
| 代理商： | 5962-0924001VXC |
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ADC
TI ADS5400
CLKIN
VCO
REF
CDC
(ClockDistributionChip)
Ex : TICDCM7005
LVPECL
or
LVCMOS
1000 MHz (To TransmitDAC )
125 MHz (ToDSP )
250 MHz (ToFPGA )
ToOther
BoardMaster
ReferenceClock
( HighorLowJitter)
10 MHz
1000 MHz
LowJitterOscillator
SAW
LVPECL
XFMR
AMP
Thisisageneralblockdiagramexample: ConsultthedatasheetoftheCDCM7005 forproperschematic
andforspecificationsregardingallowableinputandoutputfrequencyandamplituderanges .
AMP and /orBPFoptional , dependingonjitterrequirements
LowJitterClockDistribution
SLAS669B
– SEPTEMBER 2010 – REVISED MAY 2011
Figure 37 represents a scenario where an LVPECL output is used from a TI CDCM7005 with the clock signal
path optimized for maximum amplitude and minimum jitter. The jitter of this setup is difficult to estimate and
requires a careful phase noise analysis of the clock path. The BPF (and possibly a low-cost amplifier because of
insertion loss in the BPF) can improve the jitter between the CDC and ADC when the jitter provided by the CDC
is still not adequate. The total jitter at the CDCM7005 output depends heavily on the phase noise of the VCXO
selected. If it is determined that the jitter from the CDCM7005 with a VCXO is sufficient without further
conditioning, it is possible to clock the ADS5400 directly from the CDCM7005 using differential LVPECL outputs
(see the CDCM7005 data sheet for the exact schematic). A careful analysis of the required jitter and of the
components involved is recommended before determining the proper approach.
Figure 37. Clock Source Diagram
36
Copyright
2010–2011, Texas Instruments Incorporated
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