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| 型號(hào)： | 5962-0924001VXC |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP100 |
| 封裝： | HERMETIC SEALED, CERAMIC, QFP-100 |
| 文件頁數(shù)： | 14/46頁 |
| 文件大小： | 1109K |
| 代理商： | 5962-0924001VXC |
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SLAS669B
– SEPTEMBER 2010 – REVISED MAY 2011
Table 10. Serial Register 0x04 (Read or Write)
Address (hex)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0x04
Analog Offset Control bits
<7:0>
Defaults
factory set
BIT
<7:0>
Analog Offset control continued (least significant bits of 9-bit
word)
All 9-bits in this adjustment in address 0x03 and 0x04 set to 0 0000
0000 = -30mV (TBD)
All 9-bits in this adjustment in address 0x03 and 0x04 set to 1 1111
1111 = +30mV (TBD)
Step adjustment resolution is 120uV (or 1/4 LSB). Adjustments can be
used for calibration of analog signal path offset (for instance offset
error induced outside of the ADC) or to match multiple ADC offsets.
The default setting for this register is factory set to provide ~0mV of
ADC offset in the output codes and is unique for each device.
Performance of the ADC is not specified across the entire offset
control range. Some performance degradation is expected as larger
offsets are programmed.
Table 11. Serial Register 0x05 (Read or Write)
Address (hex)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Stagger
0x05
Temp Sensor
Powerdown
reserved
Sync Mode
Data Format
Reference
0
Output
Defaults
0
1
0
BIT
<0>
RESERVED
0
set to 0 if writing this register
1
do not set to 1
BIT
<1>
Stagger Output Bus
0
Output bus A and B aligned
1
Output bus A and B staggered (see timing diagrams)
BIT
<2>
Enable External Reference
0
Enable internal reference
1
Enable external reference
BIT
<3>
Set Data Output Format
0
Enable offset binary
1
Enable two's complement
BIT
<4>
Set Sync Mode
0
Disable data synchronization mode
1
Enable data synchronization mode
When enabled, the OVR pin(s) are replaced with SYNC output
signal(s). The SYNC output signal is time-aligned with the output data
matching the corresponding input sample and RESET input pulse
BIT
<5>
RESERVED
Copyright
2010–2011, Texas Instruments Incorporated
21
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