參數(shù)資料
型號： 4571
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
中文描述： 單芯片4位微機(jī)的CMOS
文件頁數(shù)： 51/126頁
文件大?。?/td> 1627K
代理商： 4571
Rev.1.02
May 25, 2007
Page 30 of 124
REJ03B0179-0102
4571 Group
Note 1.“R” represents read enabled, and “W” represents write enabled.
Note 2.This function is valid only when the INT0 pin/timer 1 control is enabled (I10 =“1”) and the timer 1 count start synchronous circuit is
selected (W53 =“1”).
Note 3.This function is valid only when the INT0 pin/timer 1 control is enabled (I10 =“1”).
Table 17 Timer control registers
Timer control register PA
at reset : 002
at RAM back-up : 002
W
TPAA
PA1
Prescaler count source selection bit
0
Instruction clock (INSTCK)
1
Instruction clock divided by 4 (INSTCK/4)
PA0
Prescaler control bit
0
Stop (state initialized)
1Operating
Timer control register W1
at reset : 00002
at RAM back-up : state retained
R/W
TAW1/TW1A
W13
Timer 1 count auto-stop circuit selection bit
(Note 2)
0
Timer 1 count auto-stop circuit not selected
1
Timer 1 count auto-stop circuit selected
W12 Timer 1 control bit
0
Stop (state retained)
1Operating
Timer 1 count source selection bits
W11 W10
Count source
W11
0
PWM signal (PWMOUT)
0
1
Prescaler output (ORCLK)
1
0
System clock (STCK)
W10
1
CNTR0 input
Timer control register W2
at reset : 00002
at RAM back-up : state retained
R/W
TAW2/TW2A
W23 CNTR0 pin function selection bit
0
Timer 1 underflow signal divided by 2 output
1
Timer 2 underflow signal divided by 2 output
W22 Timer 2 control bit
0
Stop (state retained)
1Operating
Timer 2 count source selection bits
W21 W20
Count source
W21
0
PWM signal (PWMOUT)
0
1
Prescaler output (ORCLK)
1
0
System clock (STCK)
W20
1
Timer 1 underflow signal (T1UDF)
Timer control register W3
at reset : 00002
at RAM back-up : 00002
R/W
TAW3/TW3A
W33 CNTR1 pin output control bit
0
CNTR1 pin output invalid
1
CNTR1 pin output valid
W32
PWM signal
“H” interval expansion function control bit
0
PWM signal “H” interval expansion function invalid
1
PWM signal “H” interval expansion function valid
W31 Timer 3 control bit
0
Stop (state retained)
1Operating
W30 Timer 3 count source selection bit
0XIN input
1
Prescaler output (ORCLK)/2
Timer control register W5
at reset : 00002
at RAM back-up : state retained
R/W
TAW5/TW5A
W53
Timer 1 count start synchronous circuit
selection bit (Note 3)
0
Count start synchronous circuit not selected
1
Count start synchronous circuit selected
W52 CNTR0 pin input count edge selection bit
0
Falling edge
1
Rising edge
W51
CNTR 1 pin output auto-control circuit
selection bit
0
Output auto-control circuit not selected
1
Output auto-control circuit selected
W50 D4/CNTR0 pin function selection bit
0D4 (I/O) / CNTR0 (input)
1D4 (input) /CNTR0 (I/O)
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