參數(shù)資料
型號: 4571
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
中文描述: 單芯片4位微機的CMOS
文件頁數(shù): 26/126頁
文件大?。?/td> 1627K
代理商: 4571
Rev.1.02
May 25, 2007
Page 121 of 124
REJ03B0179-0102
4571 Group
Note 1. If the rising time exceeds the maximum rating value, connect a capacitor between the RESET pin and Vss at the shortest
distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating voltage.
Fig 71. System clock (STCK) operating condition map
Table 27 Recommended operating conditions 2 (Ta = –20
°C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted)
Symbol
Parameter
Conditions
Limits
Unit
Min.
Typ.
Max.
f(XIN)
Oscillation frequency
(with a ceramic resonator)
Through mode
VDD = 4.0 V to 5.5 V
6
MHz
VDD = 2.7 V to 5.5 V
4.4
VDD = 2.0 V to 5.5 V
2.2
VDD = 1.8 V to 5.5 V
1.1
Internal frequency divided
by 2
VDD = 2.7 V to 5.5 V
6
VDD = 2.0 V to 5.5 V
4.4
VDD = 1.8 V to 5.5 V
2.2
Internal frequency divided
by 4, 8
VDD = 2.0 V to 5.5 V
6
VDD = 1.8 V to 5.5 V
4.4
f(XIN)
Oscillation frequency
(with an external clock input)
Through mode
VDD = 4.0 V to 5.5 V
4.8
MHz
VDD = 2.7 V to 5.5 V
3.2
VDD = 2.0 V to 5.5 V
1.6
VDD = 1.8 V to 5.5 V
0.8
Internal frequency divided
by 2
VDD = 2.7 V to 5.5 V
4.8
VDD = 2.0 V to 5.5 V
3.2
VDD = 1.8 V to 5.5 V
1.6
Internal frequency divided
by 4, 8
VDD = 2.0 V to 5.5 V
4.8
VDD = 1.8 V to 5.5 V
3.2
f(CNTR)
Timer external input frequency CNTR0, CNTR1
f(STCK)/6
Hz
tw(CNTR)
Timer external input period
(“H” and “L” pulse width)
CNTR0, CNTR1
3/f(STCK)
s
TPON
Power-on reset circuit valid
supply voltage rising time
(Note 1)
VDD = 0
1.8V
100
s
1.1
2.2
4.4
6
1.8 2
2.7
4
5.5
Recommended
operating conditions
with a ceramic resonator
f(STCK)
[MHz]
VDD
[V]
0.8
1.6
3.2
4.8
1.8 2
2.7
4
5.5
Recommended
operating conditions
at external clock oscillation
f(STCK)
[MHz]
VDD
[V]
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