參數(shù)資料
型號: 4571
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
中文描述: 單芯片4位微機(jī)的CMOS
文件頁數(shù): 28/126頁
文件大?。?/td> 1627K
代理商: 4571
Rev.1.02
May 25, 2007
Page 123 of 124
REJ03B0179-0102
4571 Group
Voltage drop detection circuit characteristics
Note 1.The detection voltage (VRST
) is defined as the voltage when reset occurs when the supply voltage (VDD) is falling.
Note 2.The detection voltage (VRST+) is defined as the voltage when reset is released when the supply voltage (VDD) is rising from reset
occurs.
Note 3.When the supply voltage goes lower than the detection voltage (VINT), the voltage drop detection circuit interrupt request flag
(VDF) is set to “1“.
Note 4.IRST is added to IDD (power current).
Note 5.The detection time (TRST) is defined as the time until reset occurs when the supply voltage (VDD) is falling to [VRST-
0.1V].
Basic timing diagram
Table 29 Voltage drop detection circuit characteristics (Ta = –20
°C to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
Limits
Unit
Min.
Typ.
Max.
VRST-
Detection voltage
(reset occurs) (Note 1)
Ta = 25
°C1.65
V
20°CTa < 0°C1.6
2.2
0
°CTa < 50°C1.3
2.1
50
°CTa 85°C1.1
1.8
VRST+
Detection voltage
(reset release) (Note 2)
Ta = 25
°C1.75
V
20°CTa < 0°C1.7
2.3
0
°CTa < 50°C1.4
2.2
50
°CTa 85°C1.2
1.9
VINT
Detection voltage
(Interrupt occurs) (Note 3)
Ta = 25
°C1.85
V
20°CTa < 0°C1.8
2.4
0
°CTa < 50°C1.5
2.3
50
°CTa 85°C1.3
2.2
VRST+
VRST-
Detection voltage hysteresis
0.1
V
IRST
Voltage drop detection circuit
operation current (Note 4)
VDD = 5V
40
80
A
VDD = 3V
20
40
VDD = 1.65V
7
15
TRST
Detection time (Note 5)
VDD → (VRST-
0.1V)
0.2
1.2
ms
System clock
STCK
Port output
D0 to D4
P00 to P03
P10 to P13
P20,P21
P30,P31,C
Port input
D0 to D4
P00 to P03
P10 to P13
P20,P21
P30,P31,K
Interrupt input
INT0, INT1
Parameter
Pin name
Machine cycle
Mi
Mi + 1
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