376 EMBEDDED PROCESSOR
9.0 REVISION HISTORY
The sections significantly revised since version -003 are:
Section 1.0
Added FLT pin.
Section 4.4
Added description of FLOAT operation and ONCE Mode. Figure 4.20 is new.
Section 4.6
Added revision identifier information for change to CHMOS IV manufacturing process.
Both packages now specified for 0
§
C–115
§
C case temperature operation. Thermal resist-
ance values changed.
Section 5.0
Section 6.3
I
CC
Max. specifications changed from 400 mA (cold) and 360 mA (hot) to 275 mA (cold, 16
MHz) and 305 mA (cold, 20 MHz).
Section 6.4
HLDA Valid Delay, t
14
, min. changed from 6 ns to 4 ns. Added 20 MHz A.C. specifications in
Table 6.5. Replaced Capacitive Derating Curves in Figures 6.8–6.10 to reflect new manufac-
turing process. Replaced I
CC
vs. Frequency data (Figure 6.11) to reflect new specifications.
The sections significantly revised since version -002 are:
Section 1.0
Modified table 1.1. to list pins in alphabetical order.
The sections significantly revised since version -001 are:
Section 2.0
Figure 2.0 was updated to show the 16-bit registers SI, DI, BP and SP.
Section 2.1
Figure 2.2 was updated to show the correct bit polarity for bit 4 in the CR0 register.
Section 2.1
Tables 2.1 and 2.2 were updated to include additional information on the EFLAGs and CR0
registers.
Section 2.3
Figure 2.3 was updated to more accurately reflect the addressing mechanism of the 80376.
Section 2.6
In the subsection
Maskable Interrupt
a paragraph was added to describe the effect of
interrupt gates on the IF EFLAGs bit.
Section 2.8
Table 2.7 was updated to reflect the correct power up condition of the CR0 register.
Section 2.10
Figure 2.6 was updated to show the correct bit positions of the BT, BS and BD bits in the
DR6 register.
Section 3.0
Figure 3.1 was updated to clearly show the address calculation process.
Section 3.2
The subsection
DESCRIPTORS
was elaborated upon to clearly define the relationship be-
tween the linear address space and physical address space of the 80376.
Section 3.2
Figures 3.3 and 3.4 were updated to show the AVL bit field.
Section 3.3
The last sentence in the first paragraph of subsection
PROTECTION AND I/O PERMIS-
SION BIT MAP
was deleted. This was an incorrect statement.
Section 4.1
In the Subsection
ADDRESS BUS (BHE, BLE, A
23
–A
1
last sentence in the first paragraph
was updated to reflect the numerics operand addresses as 8000FCH and 8000FEH. Be-
cause the 80376 sometimes does a double word I/O access a second access to 8000FEH
can be seen.
Section 4.1
The Subsection
Hold Lantencies
was updated to describe how 32-bit and unaligned ac-
cesses are internally locked but do not assert the LOCK signal.
Section 4.2
Table 4.6 was updated to show the correct active data bits during a BLE assertion.
94