參數(shù)資料
型號(hào)： 376
廠商： Intel Corp.
英文描述： DIODE SCHOTTKY DUAL-DUAL SERIES 30V 200mW 0.38V-vf 200mA-IFM 1mA-IF 0.2uA-IR SOT-363 3K/REEL
中文描述： 376TM，高性能32位嵌入式處理器
文件頁(yè)數(shù)： 38/95頁(yè)
文件大?。?/td> 1293K
代理商： 376
376 EMBEDDED PROCESSOR
INTERRUPT SIGNALS (INTR, NMI, RESET)
The following descriptions cover inputs that can in-
terrupt or suspend execution of the processor’s cur-
rent instruction stream.
Maskable Interrupt Request (INTR)
When asserted, this input indicates a request for in-
terrupt service, which can be masked by the 80376
Flag Register IF bit. When the 80376 responds to
the INTR input, it performs two interrupt acknowl-
edge bus cycles and, at the end of the second,
latches an 8-bit interrupt vector on D
7
–D
0
to identify
the source of the interrupt.
INTR is an active HIGH, level-sensitive asynchro-
nous signal. Setup and hold times, t
27
and t
28
, rela-
tive to the CLK2 signal must be met to guarantee
recognition at a particular clock edge. To assure rec-
ognition of an INTR request, INTR should remain
active until the first interrupt acknowledge bus cycle
begins. INTR is sampled at the beginning of every
instruction. In order to be recognized at a particular
instruction boundary, INTR must be active at least
eight CLK2 clock periods before the beginning of the
execution of the instruction. If recognized, the 80376
will begin execution of the interrupt.
Non-Maskable Interrupt Request (NMI)
This input indicates a request for interrupt service
which cannot be masked by software. The non-
maskable interrupt request is always processed ac-
cording to the pointer or gate in slot 2 of the interrupt
table. Because of the fixed NMI slot assignment, no
interrupt acknowledge cycles are performed when
processing NMI.
NMI is an active HIGH, rising edge-sensitive asyn-
chronous signal. Setup and hold times, t
27
and t
28
,
relative to the CLK2 signal must be met to guarantee
recognition at a particular clock edge. To assure rec-
ognition of NMI, it must be inactive for at least eight
CLK2 periods, and then be active for at least eight
CLK2 periods before the beginning of the execution
of an instruction.
Once NMI processing has begun, no additional
NMI’s are processed until after the next IRET in-
struction, which is typically the end of the NMI serv-
ice routine. If NMI is re-asserted prior to that time,
however, one rising edge on NMI will be remem-
bered for processing after executing the next IRET
instruction.
Interrupt Latency
The time that elapses before an interrupt request is
serviced (interrupt latency) varies according to sev-
eral factors. This delay must be taken into account
by the interrupt source. Any of the following factors
can affect interrupt latency:
1. If interrupts are masked, and INTR request will
not be recognized until interrupts are reenabled.
2. If an NMI is currently being serviced, an incoming
NMI request will not be recognized until the 80376
encounters the IRET instruction.
3. An interrupt request is recognized only on an in-
struction boundary of the 80376
Execution Unit
except for the following cases:
D Repeat string instructions can be interrupted
after each iteration.
D If the instruction loads the Stack Segment reg-
ister, an interrupt is not processed until after
the following instruction, which should be an
ESP load. This allows the entire stack pointer
to be loaded without interruption.
D If an instruction sets the interrupt flag (enabling
interrupts), an interrupt is not processed until
after the next instruction.
The longest latency occurs when the interrupt re-
quest arrives while the 80376 processor is exe-
cuting a long instruction such as multiplication, di-
vision or a task-switch.
4. Saving the Flags register and CS:EIP registers.
5. If interrupt service routine requires a task switch,
time must be allowed for the task switch.
6. If the interrupt service routine saves registers that
are not automatically saved by the 80376.
RESET
This input signal suspends any operation in progress
and places the 80376 in a known reset state. The
80376 is reset by asserting RESET for 15 or more
CLK2 periods (80 or more CLK2 periods before re-
questing self-test). When RESET is active, all other
input pins except FLT are ignored, and all other bus
pins are driven to an idle bus state as shown in Ta-
ble 4.4. If RESET and HOLD are both active at a
point in time, RESET takes priority even if the 80376
was in a Hold Acknowledge state prior to RESET
active.
RESET is an active HIGH, level-sensitive synchro-
nous signal. Setup and hold times, t
25
and t
26
, must
be met in order to assure proper operation of the
80376.
38
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
376 制造商:Pro-Signal 功能描述:; Supply Voltage:28VDC; Lamp Base Type:M
37-6.8 制造商:Distributed By MCM 功能描述:Resistor 1/2W 6.8 Ohm Flameproof, Bag of 20 制造商:MCM 功能描述:1/2 Watt Flameproof Resistors, Resistance: 6.8 Ohm, Tolerance: 5 %, Quantity: 20 per bag
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376/377-1ZM 制造商:Rayovac 功能描述:SILVER ELECTRONIC BTRY 1PK MERCURY FREE
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