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| 型號： | 376 |
| 廠商： | Intel Corp. |
| 英文描述： | DIODE SCHOTTKY DUAL-DUAL SERIES 30V 200mW 0.38V-vf 200mA-IFM 1mA-IF 0.2uA-IR SOT-363 3K/REEL |
| 中文描述： | 376TM，高性能32位嵌入式處理器 |
| 文件頁數(shù)： | 31/95頁 |
| 文件大?。?/td> | 1293K |
| 代理商： | 376 |
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376 EMBEDDED PROCESSOR
TASK SWITCHING
A very important attribute of any multi-tasking oper-
ating system is its ability to rapidly switch between
tasks or processes. The 80376 directly supports this
operation by providing a task switch instruction in
hardware. The 80376 task switch operation saves
the entire state of the machine (all of the registers,
address space, and a link to the previous task),
loads a new execution state, performs protection
checks, and commences execution in the new task.
Like transfer of control by gates, the task switch op-
eration is invoked by executing an inter-segment
JMP or CALL instruction which refers to a Task
State Segment (TSS), or a task gate descriptor in
the GDT or LDT. An INT n instruction, exception,
trap or external interrupt may also invoke the task
switch operation if there is a task gate descriptor in
the associated IDT descriptor slot. For simple appli-
cations, the TSS and task switching may not be
used. The TSS or task switch will not be used or
occur if no task gates are present in the GDT, LDT
or IDT.
The TSS descriptor points to a segment (see Figure
3.7) containing the entire 80376 execution state. A
task gate descriptor contains a TSS selector. The
limit of an 80376 TSS must be greater than 64H, and
can be as large as 16 Mbytes. In the additional TSS
space, the operating system is free to store addition-
al information as the reason the task is inactive, the
time the task has spent running, and open files be-
longing to the task. For maximum performance, TSS
should start on an even address.
Each Task must have a TSS associated with it. The
current TSS is identified by a special register in the
80376 called the Task State Segment Register (TR).
This register contains a selector referring to the task
state segment descriptor that defines the current
TSS. A hidden base and limit register associated
with the TSS descriptor is loaded whenever TR is
loaded with a new selector. Returning from a task is
accomplished by the IRET instruction. When IRET is
executed, control is returned to the task which was
interrupted. The current executing task’s state is
saved in the TSS and the old task state is restored
from its TSS.
Several bits in the flag register and CR0 register give
information about the state of a task which is useful
to the operating system. The Nested Task bit, NT,
controls the function of the IRET instruction. If NT
e
0 the IRET instruction performs the regular return. If
NT
e
1, IRET performs a task switch operation
back to the previous task. The NT bit is set or reset
in the following fashion:
When a CALL or INT instruction initiates a task
switch, the new TSS will be marked busy and
the back link field of the new TSS set to the old
TSS selector. The NT bit of the new task is set
by CALL or INT initiated task switches. An inter-
rupt that does not cause a task switch will clear
NT (The NT bit will be restored after execution
of the interrupt handler). NT may also be set or
cleared by POPF or IRET instructions.
The 80376 task state segment is marked busy by
changing the descriptor type field from TYPE 9 to
TYPE 0BH. Use of a selector that references a busy
task state segment causes an exception 13.
The coprocessor’s state is not automatically saved
when a task switch occurs. The Task Switched Bit,
TS, in the CR0 register helps deal with the coproces-
sor’s state in a multi-tasking environment. Whenever
the 80376 switches tasks, it sets the TS bit. The
80376 detects the first use of a processor extension
instruction after a task switch and causes the proc-
essor extension not available exception 7. The ex-
ception handler for exception 7 may then decide
whether to save the state of the coprocessor.
The T bit in the 80376 TSS indicates that the proc-
essor should generate a debug exception when
switching to a task. If T
e
1 then upon entry to a
new task a debug exception 1 will be generated.
240182–15
I/O Ports Accessible 2
x
9, 12, 13, 15, 20
x
24, 27, 33, 34, 40, 41, 48, 50, 52, 53, 58
x
60, 62, 63, 96
x
127
Figure 3.8. Sample I/O Permission Bit Map
31
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 376 | 制造商:Pro-Signal 功能描述:; Supply Voltage:28VDC; Lamp Base Type:M |
| 37-6.8 | 制造商:Distributed By MCM 功能描述:Resistor 1/2W 6.8 Ohm Flameproof, Bag of 20 制造商:MCM 功能描述:1/2 Watt Flameproof Resistors, Resistance: 6.8 Ohm, Tolerance: 5 %, Quantity: 20 per bag |
| 37-6.8K | 制造商:Distributed By MCM 功能描述:Resistor 1/2W 6.8K Ohm Flameproof, Bag of 20 制造商:MCM 功能描述:RESISTOR 1/2W 6.8K OHM FLAMPRF20 PER BAG |
| 376/377-1ZM | 制造商:Rayovac 功能描述:SILVER ELECTRONIC BTRY 1PK MERCURY FREE |
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