參數(shù)資料
型號： 376
廠商： Intel Corp.
英文描述： DIODE SCHOTTKY DUAL-DUAL SERIES 30V 200mW 0.38V-vf 200mA-IFM 1mA-IF 0.2uA-IR SOT-363 3K/REEL
中文描述： 376TM，高性能32位嵌入式處理器
文件頁數(shù)： 39/95頁
文件大?。?/td> 1293K
代理商： 376
376 EMBEDDED PROCESSOR
Table 4.4. Pin State (Bus Idle) during RESET
Pin Name
Signal Level during RESET
ADS
1
D
15
–D
0
Float
BHE, BLE
0
A
23
–A
1
1
W/R
0
D/C
1
M/IO
0
LOCK
1
HLDA
0
4.2 Bus Transfer Mechanism
All data transfers occur as a result of one or more
bus cycles. Logical data operands of byte and word
lengths may be transferred without restrictions on
physical address alignment. Any byte boundary may
be used, although two physical bus cycles are per-
formed as required for unaligned operand transfers.
The 80376 processor address signals are designed
to simplify external system hardware. BHE and BLE
provide linear selects for the two bytes of the 16-bit
data bus.
Byte Enable outputs BHE and BLE are asserted
when their associated data bus bytes are involved
with the present bus cycle, as listed in Table 4.5.
Table 4.5. Byte Enables and Associated
Data and Operand Bytes
Byte Enable
Associated Data Bus Signals
BHE
BLE
D
15
–D
8
(Byte 1DMost Significant)
D
7
–D
0
(Byte 0DLeast Significant)
Each bus cycle is composed of at least two bus
states. Each bus state requires one processor clock
period. Additional bus states added to a single bus
cycle are called wait states. See
Bus Functional
Description
for additional information.
4.3 Memory and I/O Spaces
Bus cycles may access physical memory space or
I/O space. Peripheral devices in the system may ei-
ther be memory-mapped, or I/O-mapped, or both.
As shown in Figure 4.3, physical memory addresses
range from 000000H to 0FFFFFFH (16 Mbytes) and
I/O
addresses
from
(64 Kbytes). Note the I/O addresses used by the
automatic I/O cycles for coprocessor communica-
tion are 8000F8H to 8000FFH, beyond the address
range of programmed I/O, to allow easy generation
of a coprocessor chip select signal using the A
23
and M/IO signals.
000000H
to
00FFFFH
OPERAND ALIGNMENT
With the flexibility of memory addressing on the
80376, it is possible to transfer a logical operand
that spans more than one physical Dword or word of
memory or I/O. Examples are 32-bit Dword or 16-bit
word operands beginning at addresses not evenly
divisible by 2.
Operand alignment and size dictate when multiple
bus cycles are required. Table 4.6 describes the
transfer cycles generated for all combinations of log-
ical operand lengths and alignment.
Table 4.6. Transfer Bus Cycles
for Bytes, Words and Dwords
Byte-Length of Logical Operand
1
2
4
Physical Byte
Address in
Memory
(Low-Order
Bits)
xx
00
01
10
11
00
01
10
11
Transfer
Cycles
b
w
lb,
hb
w
hb,
l,b
lw,
hw
hb, hw, mw,
lb,
lw
mw
hb,
lb
Key:
b
e
byte transfer
w
e
word transfer
l
e
low-order portion
m
e
mid-order portion
x
e
don’t care
h
e
high-order portion
39
相關(guān)PDF資料
PDF描述
37LV128-TISN DIODE ZENER SINGLE 200mW 2.7Vz 5mA-Izt 0.0741 20uA-Ir 1 SOD-323 3K/REEL
37LV128-TL DIODE ZENER SINGLE 150mW 2.7Vz 5mA-Izt 0.074 20uA-Ir 1 SOD-523 3K/REEL
37LV128-TP DIODE/SM, ZEN 30V .5MA 0.41W +/-5% SOD-123
37LV128-TSN 36K, 64K, and 128K Serial EPROM Family
37LV128-IL 36K, 64K, and 128K Serial EPROM Family
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
376 制造商:Pro-Signal 功能描述:; Supply Voltage:28VDC; Lamp Base Type:M
37-6.8 制造商:Distributed By MCM 功能描述:Resistor 1/2W 6.8 Ohm Flameproof, Bag of 20 制造商:MCM 功能描述:1/2 Watt Flameproof Resistors, Resistance: 6.8 Ohm, Tolerance: 5 %, Quantity: 20 per bag
37-6.8K 制造商:Distributed By MCM 功能描述:Resistor 1/2W 6.8K Ohm Flameproof, Bag of 20 制造商:MCM 功能描述:RESISTOR 1/2W 6.8K OHM FLAMPRF20 PER BAG
376/377-1ZM 制造商:Rayovac 功能描述:SILVER ELECTRONIC BTRY 1PK MERCURY FREE
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*