376 EMBEDDED PROCESSOR
2.2 Instruction Set
The instruction set is divided into nine categories of
operations:
Data Transfer
Arithmetic
Shift/Rotate
String Manipulation
Bit Manipulation
Control Transfer
High Level Language Support
Operating System Support
Processor Control
These 80376 processor instructions are listed in Ta-
ble 8.1
80376 Instruction Set and Clock Count
Summary
.
All 80376 processor instructions operate on either 0,
1, 2 or 3 operands; an operand resides in a register,
in the instruction itself, or in memory. Most zero op-
erand instructions (e.g. CLI, STI) take only one byte.
One operand instructions generally are two bytes
long. The average instruction is 3.2 bytes long.
Since the 80376 has a 16-byte prefetch instruction
queue an average of 5 instructions can be pre-
fetched. The use of two operands permits the follow-
ing types of common instructions:
Register to Register
Memory to Register
Immediate to Register
Memory to Memory
Register to Memory
Immediate to Memory
The operands are either 8-, 16- or 32-bit long.
2.3 Memory Organization
Memory on the 80376 is divided into 8-bit quantities
(bytes), 16-bit quantities (words), and 32-bit quanti-
ties (dwords). Words are stored in two consecutive
bytes in memory with the low-order byte at the low-
est address. Dwords are stored in four consecutive
bytes in memory with the low-order byte at the low-
est address. The address of a word or Dword is the
byte address of the low-order byte. For maximum
performance word and dword values should be at
even physical addresses.
In addition to these basic data types the 80376 proc-
essor supports segments. Memory can be divided
up into one or more variable length segments, which
can be shared between programs.
ADDRESS SPACES
The 80376 has three types of address spaces:
logi-
cal, linear,
and
physical.
A
logical
address (also
known as a
virtual
address) consists of a selector
and an offset. A selector is the contents of a seg-
ment register. An offset is formed by summing all of
the addressing components (BASE, INDEX, and
DISPLACEMENT), discussed in Section 2.4
Ad-
dressing Modes,
into an effective address.
Every selector has a
logical base
address associat-
ed with it that can be up to 32 bits in length. This 32-
bit
logical base
address is added to either a 32-bit
offset address or a 16-bit offset address (by using
the
address length prefix
)to form a final 32-bit
lin-
ear
address. This final
linear
address is then trun-
cated so that only the lower 24 bits of this address
are used to address the 16 Mbytes physical memory
address space. The
logical base
address is stored
in one of two operating system tables (i.e. the Local
Descriptor Table or Global Descriptor Table).
Figure 2.3 shows the relationship between the vari-
ous address spaces.
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