參數(shù)資料
型號： 33742S
廠商： Motorola, Inc.
元件分類： CAN
英文描述： System Basis Chip (SBC) with Enhanced High-Speed CAN Transceiver
中文描述： 系統(tǒng)基礎芯片的增強型（SBC）的高速CAN收發(fā)器
文件頁數(shù)： 44/52頁
文件大小： 1087K
代理商： 33742S
33742
44
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Figure 27. HS Operation When Cyclic Sense Is Selected
——————————————————
Low Power Control Register (LPC)
Tables 30
through
34
contain various Low Power Control
Register information. The LPC register controls:
The state of HS in Stop and Sleep modes (HS
permanently OFF or HS cyclic).
Enable or disable of the forced wake-up function (33742
automatic wake-up after time spent in Sleep or Stop
modes; time is defined by the TIM2 subregister).
Enable or disable the sense of the wake-up inputs (Lx) at
the sampling point of the Cyclic Sense period (LX2HS bit).
(Refer to
Reset Control Register (RCR) on page 40
for
details of the LPC register setup required for proper cyclic
sense or direct wake-up operation.
The LPC register also reports the CANH and RXD
diagnostic.
Cyclic Sense Timing, OFF Time
time
HS
Sample
10
μ
s
HS OFF
HS ON
Lx Sampling Point
Cyclic Sense Timing,
ON Time
Table 29. TIM2 Control Bits
CSP2 CSP1 CSP0
Cyclic Sense
Timing (ms)
Parameter
0
0
0
4.6
Cyclic Sense/FWU Timing 1
0
0
1
9.25
Cyclic Sense/FWU Timing 2
0
1
0
18.5
Cyclic Sense/FWU Timing 3
0
1
1
37
Cyclic Sense/FWU Timing 4
1
0
0
74
Cyclic Sense/FWU Timing 5
1
0
1
95.5
Cyclic Sense/FWU Timing 6
1
1
0
191
Cyclic Sense/FWU Timing 7
1
1
1
388
Cyclic Sense/FWU Timing 8
Table 30. Low Power Control Register
LPC
R/W
D3
D2
D1
D0
$110b
W
LX2HS
FWU
CAN-INT
HSAUTO
R
CANH2VDD CANH2BAT CANH2GND
RXPR
Reset
Value
–
0
0
0
0
Reset
Condition
(Write)
(Note 62)
–
POR,
NR2R, N2R,
STB2R,
STO2R
POR,
NR2R, N2R,
STB2R,
STO2R
POR,
NR2R, N2R,
STB2R,
STO2R
POR,
NR2R, N2R,
STB2R,
STO2R
Notes
62.
See
Table 8
, page 38, for definitions of reset conditions.
Table 31. LX2HS Control Bits
Value
Wake-Up Inputs Supplied by HS
0
No.
1
Yes. Lx inputs sensed at sampling point.
Table 32. HSAUTO Control Bits
Value
Auto-Timing HS in Sleep and Stop Modes
0
OFF.
1
ON, HS Cyclic, period defined in TIM2 subregister.
Table 33. CAN-INT Control Bits
Value
(Note 63)
Description
0
Interrupt as soon as CAN bus failure detected.
1
Interrupt when CAN bus failure detected and fully
identified.
Notes
63.
If CAN-INT is at 0, any undetermined CAN failure will be
latched in the CAN register (bit D1: CAN-UF) and can be
accessed by SPI (refer to
CAN Register (CAN) on page 40
).
After reading the CAN register or setting CAN-INT to 1, it will
be cleared automatically. The existence of CAN-UF always
has priority over clearing, meaning that a further undetermined
CAN failure does not allow clearing the CAN-UF bit.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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