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| 型號： | 33742S |
| 廠商： | Motorola, Inc. |
| 元件分類： | CAN |
| 英文描述： | System Basis Chip (SBC) with Enhanced High-Speed CAN Transceiver |
| 中文描述： | 系統(tǒng)基礎(chǔ)芯片的增強(qiáng)型（SBC）的高速CAN收發(fā)器 |
| 文件頁數(shù)： | 23/52頁 |
| 文件大小： | 1087K |
| 代理商： | 33742S |
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33742
23
Reset and Watchdog Operation
Table 3
describes watchdog and reset output modes of
operation.
RST
is activated in the event V
DD
fall or watchdog is
not triggered.
WDOG
output is active LOW as soon as
RST
goes
LOW and stays LOW as long as the watchdog is not properly
reactivated by SPI. The
WDOG
output terminal is a push-pull
structure that can drive external components of the application;
for instance, to signal MCU wrong operation.
Figure 9
illustrates the device behavior in the event the TIM1
register in not properly accessed. In this case a software reset
occurs, and the
WDOG
terminal is set LOW until the TIM1
register is properly accessed.
Figure 9.
RST
and
WDOG
Output Operation
Wake-Up Capabilities
Several wake-up capabilities are available to the 33742
when it is in Sleep or Stop mode. When a wake-up has
occurred, the wake-up event is stored in the Wake-Up Register
(WUR) or the CAN register. The MCU can then access the
wake-up source. The wake-up options are selectable through
SPI while the 33742 is in Normal or Standby mode and prior to
entering low power mode (Sleep or Stop mode). When a wake-
up occurs from Sleep mode, the 33742 activates V
DD
. It
generates an interrupt if wake-up occurs from Stop mode.
Wake-Up from Wake-Up Inputs (L0:L3) Without Cyclic
Sense
The wake-up lines are dedicated to sense the state of
external switches and if changes occur to wake up the MCU (in
Sleep or Stop modes). Wake-up terminals L0:L3 are able to
handle 40 VDC. The internal threshold is 3.0 V typical and
these inputs can be used as an input port expander. The wake-
up input states are read through SPI (WUR register).
In order to select and activate direct wake-up from the L0:L3
inputs, the WUR register must be configured with the
appropriate level sensitivity. Additionally, the Low Power
Control (LPC) Register must be configured with 0xx0 data (bits
LX2HS and HSAUTO are set to 0).
Level sensitivity is selected by the WUR register. Level
sensitivity is configured by L0:L3 input pairs: L0 and L1 level
sensitivity are configured together, while L2 and L3 are
configured together.
Cyclic Sense Wake-Up (Cyclic Sense Timer and Wake-Up
Inputs L0:L3)
The 33742 can wake up upon state change of one of the four
wake-up input lines (L0:L3) while the external pullup or
pulldown resistor of the switches associated with the wake-up
input lines are biased with HS V
SUP
switch. The HS switch is
activated in Sleep or Stop modes from an internal timer. Cyclic
Sense and Forced Wake-Up are exclusive. If Cyclic Sense is
enabled, Forced Wake-Up cannot be enabled.
In order to select and activate the cyclic sense wake-up from
the L0:L3 inputs, the WUR register must be configured with the
appropriate level sensitivity, and the LPC register must be
configured with 1xx1 data (bit LX2HS set at 1 and bit HSAUTO
set at 1). The wake-up mode selection (direct or cyclic sense) is
valid for all four wake-up inputs.
Table 3. Watchdog and Reset Output Operation
Events
WDOG
Output
RST
Output
Device Power-Up
LOW to HIGH
LOW to HIGH
V
DD
Normal,
Watchdog Properly Triggered
HIGH
HIGH
V
DD
<
RST
TH
HIGH
LOW
Watchdog Timeout Reached
LOW
(Note 41)
LOW
Notes
41.
WDOG
stays LOW until the TIM1 register
is properly
addressed through SPI.
RST
WDOG
V
DD
SPI
SPI
CS
Watchdog Timeout
TIM1 register addressed.
Watchdog
Period
Watchdog Clear
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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