參數(shù)資料
型號(hào)： 33742S
廠商： Motorola, Inc.
元件分類： CAN
英文描述： System Basis Chip (SBC) with Enhanced High-Speed CAN Transceiver
中文描述： 系統(tǒng)基礎(chǔ)芯片的增強(qiáng)型（SBC）的高速CAN收發(fā)器
文件頁(yè)數(shù)： 43/52頁(yè)
文件大小： 1087K
代理商： 33742S
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33742
43
Timing Register (TIM1/2)
Tables 25
through
29
contain various Timing Register
information. The TIM register is composed of two subregisters:
1. TIM1—Controls the watchdog timing selection as well as
either the watchdog window or the watchdog timeout
option (
Figure 25
and
Figure 26
, respectively). TIM1 is
selected when bit D3 is 0 (
Table 25
). Watchdog timing
characteristics are described in
Table 26
.
2. TIM2—Selects an appropriate timing for sensing the
wake-up circuitry or cyclically supplying devices by
switching the HS on or off. TIM2 is selected when bit D3
is 1 (
Table 27
).
Figure 27
, page 44, describes HS
operation when cyclic sense is selected
.
Cyclic sense
timing characteristics are described in
Table 29
, page 44.
Both subregisters also report the CANL and TXD diagnostic.
Figure 25. Window Watchdog
Figure 26. Timeout Watchdog
Table 25. TIM1 Timing and
CANL Failure Diagnostic Register
TIM1
R/W
D3
D2
D1
D0
$101b
W
0
WDW
WDT1
WDT0
R
CANL2VDD
CANL2BAT CANL2GND
TXPD
Reset
Value
–
–
0
0
0
Reset
Condition
(Write)
(Note 60)
–
–
POR,
RESET
POR,
RESET
POR,
RESET
Notes
60.
See
Table 8
, page 38, for definitions of reset conditions.
Table 26. TIM1 Control Bits
WDW WDT1 WDT0
Timing
(ms typ)
Parameter
Description
0
0
0
9.75
Watchdog
Period 1
No Window
Watchdog
0
0
1
45
Watchdog
Period 2
0
1
0
100
Watchdog
Period 3
0
1
1
350
Watchdog
Period 4
1
0
0
9.75
Watchdog
Period 1
Watchdog
Window
enabled
(Window
length is half
the Watchdog
Timing).
1
0
1
45
Watchdog
Period 2
1
1
0
100
Watchdog
Period 3
1
1
1
350
Watchdog
Period 4
Table 27. Timing Register Status Bits
Name
Value
Failure Description
CANL2VDD
0
No CANL short to V
DD
.
1
CANL short to V
DD
.
CANL2BAT
0
No CANL short to V
SUP
.
1
CANL short to V
SUP
.
CANL2GND
0
No CANL short to GND.
1
CANL short to GND.
TXPD
0
No TXD dominant
1
TXD dominant.
Table 28. TIM2 Timing and
CANL Failure Diagnostic
Register
TIM2
R/W
D3
D2
D1
D0
$101b
W
1
CSP2
CSP1
CSP0
R
CANL2VDD CANL2BAT
CANL2GND
TXPD
Reset
Value
–
–
0
0
0
Reset
Condition
(Write)
(Note 61)
–
–
POR,
RESET
POR,
RESET
POR,
RESET
Notes
61.
See
Table 8
, page 38, for definitions of reset conditions.
Watchdog Timing x 50%
Watchdog Timing x 50%
Watchdog Period
(Watchdog Timing Selected by TIM1 Bit WDW=1)
Window Closed
No Watchdog Clear Allowed
Window Open for Watchdog Clear
Watchdog Period
(Watchdog Timing Selected by TIM1 Bit WDW=0)
Window Open for Watchdog Clear
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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