參數(shù)資料
型號(hào)： 33742S
廠商： Motorola, Inc.
元件分類： CAN
英文描述： System Basis Chip (SBC) with Enhanced High-Speed CAN Transceiver
中文描述： 系統(tǒng)基礎(chǔ)芯片的增強(qiáng)型（SBC）的高速CAN收發(fā)器
文件頁(yè)數(shù)： 22/52頁(yè)
文件大?。?/td> 1087K
代理商： 33742S
33742
22
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
If no MCU wake-up occurs within the watchdog timing the
33742 activates the
RST
terminal and jumps into the Normal
Request mode. The MCU can then be initialized.
Stop Mode Enter Command
Stop mode is entered at the end of the SPI message at the
rising edge of the
CS
. (Refer to the t
CS-STOP
data in the
Dynamic Electrical Characteristics table on
page 13
.) Once
Stop mode is entered, the 33742 can wake up from the V
DD
regulator overcurrent detection. In order to allow time for the
MCU to complete the last CPU instruction, allowing the MCU to
enter its low power mode, a deglitcher time of 40
μ
s typical is
implemented.
Figure 8
, page 22, depicts the operation of entering the Stop
mode.
Figure 8. Entering Stop Mode
RST
and
WDOG
Terminals, Software Watchdog
Operations
Watchdog Software (Selectable Watchdog
Window or
Watchdog Timeout)
Watchdog software is used in the 33742 Normal and
Standby modes for monitoring the MCU. Watchdog may be
either watchdog window or watchdog timeout, selectable by
SPI (TIM1 subregister, bit WDW). Default is watchdog window.
The watchdog period may be set from 10 ms to 350 ms
(TIM1 subregister, bits WDT0 and WDT1). When watchdog
window is selected, the closed window is the first part of the
selected period, and the open window is the second part of the
period. (Refer to
Timing Register (TIM1/2)
beginning on
page 43.)
Watchdog can only be cleared within the open window time.
Any attempt to clear watchdog in the closed window will
generate a reset. Watchdog is cleared through SPI by
addressing the TIM1 subregister.
RST
Terminal Description
A reset output is available to reset the MCU. Causes of reset
are the following:
V
DD
Falling Out of Range—If V
DD
falls below the reset
threshold (V
RSTTH
), the
RST
terminal is pulled LOW until
V
DD
returns to the normal voltage.
Power-ON Reset—At 33742 power-on or wake-up from
Sleep mode, the
RST
terminal is maintained LOW until
V
DD
is within its operation range.
Watchdog Timeout—If watchdog is not cleared, the
33742 will pull the
RST
terminal LOW for the duration of
the reset time
(
t
RSTDUR
).
SPI CS
SPI Stop/Sleep
Command
33742 in Normal
or Standby mode
33742 in Stop mode.
No I
DD
over I
DD-DGLT
33742 in Stop mode.
I
DD
over I
DD-DGLT
t
CS
-STOP
t
IDD-DGLT
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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