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| 型號： | 33742S |
| 廠商： | Motorola, Inc. |
| 元件分類： | CAN |
| 英文描述： | System Basis Chip (SBC) with Enhanced High-Speed CAN Transceiver |
| 中文描述： | 系統(tǒng)基礎(chǔ)芯片的增強型（SBC）的高速CAN收發(fā)器 |
| 文件頁數(shù)： | 15/52頁 |
| 文件大?。?/td> | 1087K |
| 代理商： | 33742S |
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33742
15
DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.75 V
≤
V2
≤
5.25 V, 5.5 V
≤
V
SUP
≤
18 V, and -40
°
C
≤
T
A
≤
125
°
C. Typical values noted
reflect the approximate parameter mean at T
A
= 25
°
C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
STATE MACHINE TIMING (continued)
Delay Between
CS
Wake-Up (
CS
LOW to HIGH) and Device in Normal
Request Mode (V
DD
ON and
RST
HIGH)
Stop Mode
t
W-
CS
15
40
90
μ
s
Delay Between
CS
Wake-Up (
CS
LOW to HIGH) and First Accepted SPI
Command
Device in Stop Mode After Wake-Up
t
W-SPI
90
–
N/A
μ
s
Delay Between
INT
Pulse and First SPI Command Accepted
Device in Stop Mode After Wake-Up
t
S-1STSPI
20
–
N/A
μ
s
Delay Between Two SPI Messages Addressing the Same Register
t
2SPI
25
–
–
μ
s
V
DD
TERMINAL
Reset Delay Time
Measured at 50% of Reset Signal
t
D
4.0
–
30
μ
s
I
DD
Overcurrent to Wake-Up Deglitcher Time
(Note 34)
t
IDD-DGLT
40
55
75
μ
s
RST
TERMINAL
Reset Duration After V
DD
HIGH
33742
33742S
t
RST
DUR
t
RST
DURS
12
3.0
15
3.5
18
4.0
ms
L0, L2, L2, AND L3 INPUT TERMINALS
Wake-Up Filter Time
t
WUF
8.0
20
38
μ
s
Notes
34.
Guaranteed by design; however, it is not production tested.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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