參數(shù)資料
型號: 28F800C3
廠商: INTEL CORP
元件分類: DRAM
英文描述: 3 Volt Advanced Boot Block Flash Memory(3 V 高級快速引導(dǎo)塊閃速存儲器)
中文描述: 16M X 8 FLASH 3V PROM
文件頁數(shù): 10/59頁
文件大小: 321K
代理商: 28F800C3
28F800C3, 28F160C3, 28F320C3
E
10
PRELIMINARY
Table 2. 3 Volt Advanced+ Boot Block Pin Descriptions
(Continued)
Symbol
Type
Name and Function
V
CCQ
INPUT
I/O POWER SUPPLY:
Supplies power for input/output buffers.
[2.7 V
–3.6 V] This input should be tied directly to V
CC
.
V
PP
INPUT/
SUPPLY
PROGRAM/ERASE POWER SUPPLY:
[1.65 V–3.6 V or 11.4 V–12.6 V]
Operates as a input at logic levels to control complete device protection.
Supplies power for accelerated program and erase operations in 12 V
±
5% range. This pin cannot be left floating.
Lower
V
PP
V
PPLK
, to protect all contents
against Program and
Erase commands.
Set V
PP
= V
CC
for in-system read, program and erase operations
. In
this configuration, V
PP
can drop as low as 1.65 V to allow for resistor or
diode drop from the system supply. Note that if V
PP
is driven by a logic
signal, V
IH =
1.65. That is, V
PP
must remain above 1.65V to perform in-
system flash modifications.
Raise V
PP
to 12 V
±
5% for faster program and erase
in a production
environment. Applying 12 V
±
5% to V
PP
can only be done for a
maximum of 1000 cycles on the main blocks and 2500 cycles on the
parameter blocks.
V
PP
may be connected to 12 V for a total of 80 hours
maximum. See Section 3.4 for details on V
PP
voltage configurations.
GND
SUPPLY
GROUND:
For all internal circuitry. All ground inputs
must
be
connected.
NC
NO CONNECT:
Pin may be driven or left floating.
2.2
Block Organization
The
asymmetrically-blocked architecture that enables
system integration of code and data within a single
flash
device.
Each
block
independently of the others up to 100,000 times.
For the address locations of each block, see the
memory maps in Appendix E.
3 Volt
Advanced+
Boot
Block
is
an
can
be
erased
2.2.1
PARAMETER BLOCKS
The 3 Volt Advanced+ Boot Block flash memory
architecture includes parameter blocks to facilitate
storage of frequently updated small parameters
(i.e., data that would normally be stored in an
EEPROM). Each device contains eight parameter
blocks of 4-Kwords (4,096 words).
2.2.2
MAIN BLOCKS
After the parameter blocks, the remainder of the
array is divided into 32-Kword (32,768 words) main
blocks for data or code storage. Each 8-Mbit, 16-
Mbit, or 32-Mbit device contains 15, 31, or 63 main
blocks, respectively.
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