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參數(shù)資料
| 型號： | 28F320W30 |
| 廠商： | Intel Corp. |
| 元件分類： | DRAM |
| 英文描述： | 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30) |
| 中文描述： | 1.8伏英特爾無線閃存的3伏的I / O和SRAM（寬30） |
| 文件頁數(shù)： | 33/82頁 |
| 文件大小： | 749K |
| 代理商： | 28F320W30 |
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28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Preliminary
27
The address can either hold constant or it can increment. The device compares the incoming
address to that stored from the setup phase (WA
0
); if they match, the WSM programs the new data
word at the next sequential memory location. If they differ, the WSM jumps to the new address
location.
The program phase concludes when the host programming system writes to a different block
address; data supplied must be FFFFh. Upon program phase completion, the device enters the EFP
verify phase.
5.3.4
Verify Phase
A high percentage of the flash bits program on the first WSM pulse. However, for those cells that
do not completely program on their first attempt, EFP internal verification identifies them and
applies additional pulses as required.
The verify phase is identical in flow to that of the program phase, except that instead of
programming incoming data, the WSM compares the verify-stream data to that which was
previously programmed into the block. If the data compares correctly, the host programmer
proceeds to the next word. If not, the host waits while the WSM applies an additional pulse(s).
The host programmer must reset its initial verify-word address to the same starting location
supplied during the program phase. It then reissues each data word in the same order it did during
the program phase. Like programming, the host may write each subsequent data word to WA
0
or it
may increment up through the block addresses.
The verification phase concludes when the interfacing programmer writes to a different block
address; data supplied must be FFFFh. Upon verify phase completion, the device enters the EFP
exit phase.
5.3.5
Exit Phase
SR.7=1 indicates that the device has returned to normal operating conditions. A full status check
should be performed at this time to ensure the entire block programmed successfully. After EFP
exit, any valid CUI command can be issued.
5.4
Write Protection (V
PP
< V
PPLK
)
If the V
PP
voltage is below the V
PP
lockout threshold, word programming is prohibited. To ensure
proper word program operation, V
PP
must be set to one of the two valid V
PP
ranges. To determine
program status, poll the status register and analyze the bits.
When V
PP
is at V
PP1
, program currents are drawn through the V
CC
supply. If V
PP
is driven by a
logic signal, V
PP1
must remain above the V
PP1
minimum value in order to program erase mode.
6.0
Flash Erase Mode
6.1
Block Erase
Flash erasing is performed on a block-by-block basis; therefore, only one block may be erased at
any given time. Once a block is erased, all bits within that block will read as a logic level one (1).
相關PDF資料 |
PDF描述 |
|---|---|
| 28F6408W30 | 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30) |
| 28F640W30 | 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30) |
| 28F320B3 | SMART 3 ADVANCED BOOT BLOCK 4-, 8-, 16-, 32-MBIT FLASH MEMORY FAMILY |
| 28F640P3 | Intel StrataFlash Embedded Memory |
| 28F320C3 | 3 Volt Advanced Boot Block Flash Memory(3 V 高級快速引導塊閃速存儲器) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 28F400B3 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:SMART 3 ADVANCED BOOT BLOCK WORD-WIDE |
| 28F400B5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SMART 5 BOOT BLOCK. FLASH MEMORY FAMILY 2. 4. 8 MBIT |
| 28F400B5WG8BET | 制造商: 功能描述: 制造商:Micron Technology Inc 功能描述: 制造商:undefined 功能描述: |
| 28F400BL-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-MBlT (256K x 16. 512K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
| 28F400BL-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-MBlT (256K x 16. 512K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
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