參數(shù)資料
型號(hào): 28F320W30
廠商: Intel Corp.
元件分類(lèi): DRAM
英文描述: 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30)
中文描述: 1.8伏英特爾無(wú)線閃存的3伏的I / O和SRAM(寬30)
文件頁(yè)數(shù): 22/82頁(yè)
文件大小: 749K
代理商: 28F320W30
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
16
Preliminary
The formula t
AVQV
(ns) + t
ADD-DELAY
(ns) + t
DATA
(ns) is also known as initial access time.
Figure 6
shows the data output available and valid after four clocks from ADV# going low in the
first clock period with the LC setting at 3.
4.2.3
WAIT Signal Polarity (WT)
The WAIT signal polarity is set by register bit CR.10 (WT).
When CR.10 = 0, WAIT is active low. A
0
on the WAIT signal indicates the
asserted
state.
Figure 6. Data Output with LC Setting at Code 3
Figure 7. First Access Latency Configuration
A
MAX-0
DQ
15-0
(D/Q)
CLK (C)
CE#
ADV#
R103
Valid
Output
Valid
Output
High Z
t
ADD
t
DATA
2nd
1st
3rd
4th
5th
Valid Address
Code 3
Code 1 (Reserved)
Code 6 (Reserved)
Code 5
Code 4
Code 3
Code 2
Code 0 (Reserved)
Code 7 (Reserved)
Valid
Address
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Address [A]
ADV# [V]
DQ
15-0
[D/Q]
CLK [C]
DQ
15-0
[D/Q]
DQ
15-0
[D/Q]
DQ
15-0
[D/Q]
DQ
15-0
[D/Q]
DQ
15-0
[D/Q]
DQ
15-0
[D/Q]
DQ
15-0
[D/Q]
FREQCONF.WMF
相關(guān)PDF資料
PDF描述
28F6408W30 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30)
28F640W30 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30)
28F320B3 SMART 3 ADVANCED BOOT BLOCK 4-, 8-, 16-, 32-MBIT FLASH MEMORY FAMILY
28F640P3 Intel StrataFlash Embedded Memory
28F320C3 3 Volt Advanced Boot Block Flash Memory(3 V 高級(jí)快速引導(dǎo)塊閃速存儲(chǔ)器)
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