參數(shù)資料
型號(hào)： 28F016SA
廠商： Intel Corp.
英文描述： 16-Mbit(1 Mbit x 16, 2 Mbit x 8) FlashFile Memory(16-M位(1 M位 x 16, 2 M位 x 8) FlashFile存儲(chǔ)器)
中文描述： 16兆位（1兆位× 16，2兆位× 8）FlashFile內(nèi)存（16米位（1米位× 16，2米位× 8）FlashFile存儲(chǔ)器）
文件頁(yè)數(shù)： 8/55頁(yè)
文件大?。?/td> 849K
代理商： 28F016SA
28F016SA
E
8
SEE NEW DESIGN RECOMMENDATIONS
2.1 Lead Descriptions
Symbol
Type
Name and Function
A
0
INPUT
BYTE-SELECT ADDRESS:
Selects between high and low byte when the
device is in x8 mode. This address is latched in x8 data programs. Not
used in x16 mode (i.e., the A
0
input buffer is turned off when BYTE# is
high).
A
1
–A
15
INPUT
WORD-SELECT ADDRESSES:
Select a word within one 64-Kbyte block.
A
6
–15
selects 1 of 1024 rows, and A
1
–5
selects 16 of 512 columns. These
addresses are latched during data programs.
A
16
–A
20
INPUT
BLOCK-SELECT ADDRESSES:
Select 1 of 32 erase blocks. These
addresses are latched during data programs, block erase and lock block
operations.
DQ
0
–DQ
7
INPUT/OUTPUT
LOW-BYTE DATA BUS:
Inputs data and commands during CUI write
cycles. Outputs array, buffer, identifier or status data in the appropriate
read mode. Floated when the chip is deselected or the outputs are
disabled.
DQ
8
–DQ
15
INPUT/OUTPUT
HIGH-BYTE DATA BUS:
Inputs data during x16 data program
operations. Outputs array, buffer or identifier data in the appropriate read
mode; not used for Status Register reads. Floated when the chip is
deselected or the outputs are disabled.
CE
0
#,CE
1
#
INPUT
CHIP ENABLE INPUTS
: Activate the device’s control logic, input buffers,
decoders and sense amplifiers. With either CE
0
# or CE
1
# high, the device
is deselected and power consumption reduces to standby levels upon
completion of any current data program or block erase operations. Both
CE
0
#, CE
1
# must be low to select the device.
All timing specifications are the same for both signals. Device selection
occurs with the latter falling edge of CE
0
# or CE
1
#. The first rising edge of
CE
0
# or CE
1
# disables the device.
RP#
INPUT
RESET/POWER-DOWN:
RP# low places the device in a deep power-
down state. All circuits that burn static power, even those circuits enabled
in standby mode, are turned off. When returning from deep power-down,
a recovery time is required to allow these circuits to power-up.
When RP# goes low, any current or pending WSM operation(s) are
terminated, and the device is reset. All Status Registers return to ready
(with all status flags cleared).
OE#
INPUT
OUTPUT ENABLE:
Gates device data through the output buffers when
low. The outputs float to tri-state off when OE# is high.
NOTE:
CEx# overrides OE#, and OE# overrides WE#.
WE#
INPUT
WRITE ENABLE:
Controls
access to the CUI, Page Buffers, Data Queue
Registers and Address Queue Latches. WE# is active low, and latches
both address and data (command or array) on its rising edge.
Page Buffer addresses are latched on the falling edge of WE#.
相關(guān)PDF資料
PDF描述
28F016XD 16-Mbit Synchronous Flash Memory(16M位DRAM接口閃速存儲(chǔ)器)
28F016XS 16-Mbit Synchronous Flash Memory(16M位同步閃速存儲(chǔ)器)
28F020 5 V Bulk Erase Flash Memory(5V 整體擦寫閃速存儲(chǔ)器)
28F128J3A 3 Volt Intel StrataFlash Memory(3 V 128M位Strata閃速存儲(chǔ)器)
28F320J3A 3 Volt Intel StrataFlash Memory(3 V 32M位英特爾StrataFlash存儲(chǔ)器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
28F016SA/DD28F032SA 制造商:未知廠家 制造商全稱:未知廠家 功能描述:INFORMATION
28F016SA-070 制造商:undefined 功能描述:
28F016SC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:28F016SC - BYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY 4. 8. AND 16 MBIT
28F016SV 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-MBIT (1 MBIT x 16, 2 MBIT x 8) FlashFile MEMORY
28F016XD 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-MBIT (1 MBIT x 16) DRAM-INTERFACE FLASH MEMORY
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