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參數(shù)資料
| 型號： | 28F016SA |
| 廠商： | Intel Corp. |
| 英文描述： | 16-Mbit(1 Mbit x 16, 2 Mbit x 8) FlashFile Memory(16-M位(1 M位 x 16, 2 M位 x 8) FlashFile存儲器) |
| 中文描述： | 16兆位（1兆位× 16，2兆位× 8）FlashFile內(nèi)存（16米位（1米位× 16，2米位× 8）FlashFile存儲器） |
| 文件頁數(shù)： | 41/55頁 |
| 文件大小： | 849K |
| 代理商： | 28F016SA |
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E
NOTES:
CE# is defined as the latter of CE
0
# or CE
1
# going low or the first of CE
0
# or CE
1
# going high.
1.
Read timings during data program and block erase are the same as for normal read.
2.
Refer to command definition tables for valid address and data values.
3.
Sampled, but not 100% tested.
4.
Data program/block erase durations are measured to valid Status Register data.
5.
Word/byte program operations are typically performed with 1 programming pulse.
6.
Address and data are latched on the rising edge of WE# for all command write operations.
7.
This information will be available in a technical paper. Please call Intel’s Application Hotline or your local Intel sales office
for more information.
28F016SA
41
SEE NEW DESIGN RECOMMENDATIONS
V
V
WE# (W)
OE# (G)
RP# (P)
VPP
CEx # (E)
(V)
PODEEP
IH
IL
V
V
IH
IL
V
V
IH
IL
ADDRESSES (A)
t
WHEH
ELWL
t
t
WHDX
WHWL
t
V
V
IH
IL
t
WLWH
t
DVWH
VIH
IL
V
VIH
V
IL
PHWL
t
HIGH Z
IN
D
D
IN
IN
A
t
t
QVVL
D
IN
IL
V
PPH
V
IN
V
t
VPWH
READ EXTENDED
STATUS REGISTER DATA
DATA (D/Q)
WHQV1,2
WRITE DATA-WRITE OR
ERASE SETUP COMMAND
WRITE VALID ADDRESS
& DATA (DATA-WRITE) OR
ERASE CONFIRM COMMAND
AUTOR ERASE DELAY
V
V
RY/BY# (R)
tWHRL
t
WHGL
OH
OL
V
V
IH
IL
ADDRESSES (A)
tAVAV
AVWH
t
tWHAX
IN
A
STREAD COMPATIBLE
DIN
WRITE READ EXTENDED
REGISTER COMMAND
A=RA
NOTE 1
NOTE 2
NOTE 3
NOTE 4
D
OUT
t
RHPL
t
GHWL
NOTE 5
PPL
V
tAVAV
AVWH
t
tWHAX
0489_14
NOTES:
1.
2.
3.
4.
5.
This address string depicts data program/block erase cycles with corresponding verification via ESRD.
This address string depicts data program/block erase cycles with corresponding verification via CSRD.
This cycle is invalid when using CSRD for verification during data program/block erase operations.
CE
X
# is defined as the latter of CE
0
# or CE
1
# going low or the first of CE
0
# or CE
1
# going high.
RP# low transition is only to show t
RHPL
; not valid for above read and program cycles.
Figure 15. AC Waveforms for Command Write Operations
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F016SA/DD28F032SA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:INFORMATION |
| 28F016SA-070 | 制造商:undefined 功能描述: |
| 28F016SC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:28F016SC - BYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY 4. 8. AND 16 MBIT |
| 28F016SV | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-MBIT (1 MBIT x 16, 2 MBIT x 8) FlashFile MEMORY |
| 28F016XD | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-MBIT (1 MBIT x 16) DRAM-INTERFACE FLASH MEMORY |
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