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| 型號(hào)： | 28229-14 |
| 廠商： | MINDSPEED TECHNOLOGIES INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PBGA256 |
| 封裝： | BGA-256 |
| 文件頁(yè)數(shù)： | 246/269頁(yè) |
| 文件大小： | 3376K |
| 代理商： | 28229-14 |
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4-2
Mindspeed Technologies
28229-DSH-001-B
UTOPIA Interfaces
CX28224/5/9 Data Sheet
4.1
General UTOPIA Operation
Three primary functions are performed by the UTOPIA controller: polling, selection,
and data transfer. These functions are basically the same for both the transmit and
receive sides of the UTOPIA bus. The following example describes the transmit
functions. Refer to Figure 4-1.
The ATM layer UTOPIA controller polls the connected PHY ports by transmitting the
port addresses on the UTxAddr lines. If a port is ready to transfer data, it asserts
UTxClAv. Note that the process of polling a port does NOT result in that port being
selected to transfer data! Polling allows the controller to determine which port is ready
for data; it must then select that port before sending data. It does so by reasserting the
desired address and then asserting UtxEnb*. The PHY will then be ready to transfer
data on the UTxData lines. UTxEnb* is deasserted when the transfer is completed.
Polling can continue during the data transfer process but not during port selection. It
operates independently of the state of UTxEnb*.
To pause the data transfer, UTxEnb* can be deasserted. To continue the transfer, the
controller must reselect the port by transmitting its address one clock cycle before
asserting UTxEnb*. The controller must ensure that the cell transfer from this port has
been completed, to avoid a start-of-cell error.
4.2
UTOPIA 8-bit and 16-bit Bus Widths
The CX2822x has two bus width options, 8-bit or 16-bit, which are selected in
BusWidth, bit 2, of the MODE register (0x0202). The protocols and timing are the
same in both modes, except that 8-bit mode uses only the lower half of the data bus
(TxData[7:0] and RxData[7:0]) and parity is only generated or checked over those
bits. UTOPIA Level 2 8-bit operates up to 33 MHz and Level 2 16-bit up to 50MHz.
In 8-bit mode, each ATM cell consists of 53 bytes, as listed in Table 10-8. The first
five bytes are used for header information. The remaining bytes are used for payload.
In 16-bit mode, the cell consists of 54 bytes, as listed in Table 10-9. The first five
bytes contain header information. The sixth byte, UDF2, is required to maintain
alignment but is not read by the CX2822x. The remaining bytes are used for payload.
NOTE:
CX28224 only supports 8 bit UTOPIA.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 28230-13 | ATM SEGMENTATION AND REASSEMBLY DEVICE, PQFP208 |
| 28L0138-40R | 1 FUNCTIONS, FERRITE BEAD |
| 28L0138-70R | 1 FUNCTIONS, FERRITE BEAD |
| 28Z551 | TELECOM FILTER |
| 28Z550 | TELECOM FILTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28-22916 | 制造商:CEBEK 功能描述:PRE ASSEMBLED MODULE BOARD PRECISION TIMER 15S-60MIN |
| 28-22918 | 制造商:CEBEK 功能描述:PRE ASSEMBLED MODULE BOARD PRECISION TIMER 0.1-10 SEC |
| 28-22920 | 制造商:CEBEK 功能描述:PRE ASSEMBLED MODULE BOARD PRECISION TIMER 1-99 SEC |
| 28-22922 | 制造商:CEBEK 功能描述:PRE ASSEMBLED MODULE BOARD SEQUENTIAL TIMER 1SEC-3MIN |
| 28-22926 | 制造商:CEBEK 功能描述:PRE ASSEMBLED MODULE BOARD ON DELAY TIMER 1-60 SECOND |
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