參數(shù)資料
型號(hào): 28229-14
廠商: MINDSPEED TECHNOLOGIES INC
元件分類: 數(shù)字傳輸電路
英文描述: ATM/SONET/SDH SUPPORT CIRCUIT, PBGA256
封裝: BGA-256
文件頁(yè)數(shù): 172/269頁(yè)
文件大小: 3376K
代理商: 28229-14
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28229-DSH-001-B
Mindspeed Technologies
A
-9
CX28224/5/9 Data Sheet
IMA Version 1.1 PICS Proforma
Table A-4. IMA Data Cell (IDC) Rate Implementation Functions
Item
Protocol feature
Cond. for
Status
Pred.
Ref.
Support
IDC.1
Does the implementation ensure on transmit that a Filler cell is not
injected if an ATM layer cell is available for scheduling?
M(R-64)
Yes X No__
IDC.2
Does the implementation only check on transmit that an ATM layer
cell is available and accept that cell only when the Tx IDCC ticks?
M(R-64)
Yes X No__
IDC.3
Does the implementation only select the TRL from the set of links
whose transmit state is Active?
M(R-65)
Yes X No__
IDC.4
If there is no link in the Active state, does the implementation select
one of the links in the Usable state, if any, or one of the links in the
Unusable state otherwise?
M(R-66)
Yes X No__
IDC.5
Does the implementation only select or change the TRL during the
following situations:
during group start-up,
when the previously selected TRL's transmit state changes from
Active to any other state (e.g., Usable, Unusable, or Not In Group)
while another link’s transmit state is Active, or
when the previously selected TRL’s transmit state changes from
Usable to Unusable or Not In Group while another link’s transmit
state is Active or Usable?
M(R-67)
Yes X No__
IDC.6
Does the implementation indicate the selected or changed TRL to
the FE over the “Transmit Timing Information” field in the ICP cell?
M(R-68)
Yes X No__
IDC.7
Does the implementation derive the Tx IDCC from the selected TRL
according to Equation 1 on page 40?
M(R-69)
Yes X No__
IDC.8
When running in the CTC mode, does the implementation introduce
a stuff event every 2048 ICP, Filler and ATM layer cells on all links?
M(R-70)
Yes X No__
IDC.9
Does the implementation introduce a stuff event every 2048 ICP,
Filler and ATM layer cells on the TRL?
(O-9)
M
(CR-5)
Yes X No__
IDC.10
Does the implementation introduce stuff events on links other than
the TRL in order to compensate for the timing difference between
the TRL and the other links?
(O-9)
M
(CR-6)
Yes X No__
IDC.11
Does the implementation remove CDV attributed to the presence of
ICP cells by a mechanism equivalent to providing a small
smoothing buffer into which cells are placed after reordering and
after removing ICP cells?
M(R-71)
Yes X No__
IDC.12
If the TRL is in the Working state and the FE has, for at least 100
milliseconds, identified a given link as the TRL, does the
implementation derive the Rx IDCR using the incoming link
indicated by the FE as the TRL?
M(R-72)
Yes X No__
IDC.13
Does the implementation have an equivalent behavior to the
following: when the IMA data cell clock at the receiver ticks, one cell
is removed from the smoothing buffer; if the cell is a Filler cell, then
the Filler cell is discarded and nothing passed to the ATM layer; if
the cell is not a Filler cell, then it is passed to the ATM layer?
M(R-73)
Yes X No__
Comments:
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
28-22916 制造商:CEBEK 功能描述:PRE ASSEMBLED MODULE BOARD PRECISION TIMER 15S-60MIN
28-22918 制造商:CEBEK 功能描述:PRE ASSEMBLED MODULE BOARD PRECISION TIMER 0.1-10 SEC
28-22920 制造商:CEBEK 功能描述:PRE ASSEMBLED MODULE BOARD PRECISION TIMER 1-99 SEC
28-22922 制造商:CEBEK 功能描述:PRE ASSEMBLED MODULE BOARD SEQUENTIAL TIMER 1SEC-3MIN
28-22926 制造商:CEBEK 功能描述:PRE ASSEMBLED MODULE BOARD ON DELAY TIMER 1-60 SECOND