
28229-DSH-001-B
Mindspeed Technologies
7
-99
CX28224/5/9 Data Sheet
Registers
IMA_RX_GRPn_CELL_COUNT_LSB (Receive Cell Count LSBs)
This register contains the least significant bits of a 16 bit count of the number of ATM
layer cells received over the Receive links within the group. The register is read only.
Status clears upon read.
Group 1–16 Address
IMA_RX_GRPn_CELL_COUNT_MSB (Receive Cell Count MSBs)
This register contains the most significant bits of a 16 bit count of the number of ATM
layer cells received over the Receive links within the group. The register is read only.
Status clears upon read.
Group 1–16 Address
n=1
n=2
n=3
n=4
n=5
n=6
n=7
n=8
n=9
n=10
n=11
n=12
n=13
n=14
n=15
n=16
0x450 0x452 0x454 0x456 0x550 0x552 0x554 0x556 0x650 0x652 0x654 0x656 0x750 0x752 0x754 0x756
CX28224
Not Applicable
CX28225
Not Applicable
CX28229
Bit
Default
Name
Description
7-0
0
Receive Cell Count LSBs
Receive Group Cell Count: This field contains the least significant bits of a 16 bit
count of the number of ATM layer cells received over the Receive links within
the group. A write operation with data = 0x01 to the first address (0x450 for
Group #1, 0x452 for Group #2, etc.) transfers the state of all 16 bits of the
counter to registers that are accessible to the microprocessor bus and clears
the counter. A read operation should then be performed to read the previous
state of the counter. The first address should be read first. The second address
(0x451 for Group #1, 0x453 for Group #2, etc.) is read next. A write operation
with data = 0x00 to the first address of each group returns back to the raw
counters.
n=1
n=2
n=3
n=4
n=5
n=6
n=7
n=8
n=9
n=10
n=11
n=12
n=13
n=14
n=15
n=16
0x451 0x453 0x455 0x457 0x551 0x553 0x555 0x557 0x651 0x653 0x655 0x657 0x751 0x753 0x755 0x757
CX28224
Not Applicable
CX28225
Not Applicable
CX28229
Bit
Default
Name
Description
7-0
0
Receive Cell Count MSBs
Receive Group Cell Count: This field contains the most significant bits of a 16
bit count of the number of ATM layer cells received over the Receive links
within the group. A write operation with data = 0x01 to the first address (0x450
for Group #1, 0x452 for Group #2, etc.) transfers the state of all 16 bits of the
counter to registers that are accessible to the microprocessor bus and clears
the counter. A read operation should then be performed to read the previous
state of the counter. The first address should be read first. The second address
(0x451 for Group #1, 0x453 for Group #2, etc.) is read next. A write operation
with data = 0x00 to the first address of each group returns back to the raw
counters.