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參數(shù)資料
| 型號： | 24267A |
| 英文描述： | Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors |
| 中文描述： | “AMD的K6E家庭”，“嵌入”，“處理器的AMD PowerNow?。考夹g平臺設計指南應用指南“ |
| 文件頁數(shù)： | 46/50頁 |
| 文件大?。?/td> | 957K |
| 代理商： | 24267A |
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Appendix A—Frequently Asked Questions
AMD PowerNow! Technology Platform Design Guide for Embedded Processors
24267A/0—December 2000
Preliminary Information
Question:
Is there a need to assert RESET to perform
AMD PowerNow! technology state transitions
Answer:
No. AMD PowerNow! technology state transitions are
designed to operate dynamically and transparent to normal
system operation.
Question:
Are there any timing specifications for the length of a
AMD PowerNow! technology transition period
Answer:
The suggested duration of time for a complete
AMD PowerNow! technology transition is 200
m
s.
Hardware Implementation
Question:
If a maximum BF[2:0] boot strap option is
implemented using the recommended AND-gate logic solution,
is a multiplexer still required to guarantee a deterministic
voltage at power on
Answer:
No. The AND-gate logic solution functions as a
multiplexer. When the system power good (SPWRGD) signal is
Low, the AND-gate logic drives the regulator inputs
appropriately. When SPWRGD is High, the AND-gate logic
allows the processor VID[4:0] outputs to drive the regulator
inputs.
Question:
Can a signal other than the SPWRGD be used for
gating the CPU VID[4:0] outputs
Answer:
Yes, the PCI reset pin can also be used to gate the CPU
VID[4:0] outputs to the DC/DC regulator. However, the system
must ensure that PCIRST# is driven low when power is applied
to the processor.
Software Implementation
Question:
If the BIOS needs to access the EPMR register during
POST before the SMM handler is installed, can the EPMR
register be accessed outside of SMM
Answer:
Yes. However, the SMM handler must be installed
before SMIs initiated by AMD PowerNow! technology can be
serviced.
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