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參數(shù)資料
| 型號： | 24267A |
| 英文描述： | Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors |
| 中文描述： | “AMD的K6E家庭”，“嵌入”，“處理器的AMD PowerNow?。考夹g平臺設計指南應用指南“ |
| 文件頁數(shù)： | 23/50頁 |
| 文件大?。?/td> | 957K |
| 代理商： | 24267A |
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Dynamic Core Frequency and Core Voltage Control
17
24267A/0—December 2000
AMD PowerNow! Technology Platform Design Guide for Embedded Processors
Preliminary Information
Note:
Both the VIDC and BDC bits may be initialized at the same
time.
I
The BDC field (BVC [9:8]) should be set to 10b at POST.
All
subsequent writes to this field should ensure that these bits
remain 10b at all times.
After reading the BVC field and
setting the BDC bits during initialization, be sure to clear all
bits in the SGTC field before writing the BVC field back out.
This is required because the data returned in the SGTC field
is invalid, as it is a write-only field.
Note:
Both the VIDC and BDC bits may be initialized at the same
time.
I
Make the AMD PowerNow! Technology Descriptor Table
(see page 30) visible in the system memory map on a 16-byte
boundary within the range of 0x0C0000–0x0FFFFF or within
the first Kbyte of the extended BIOS data area.
Hardware
Initialization
Information on implementing an efficient AMD PowerNow!
technology device is provided in the “Hardware
Implementation” section, beginning on page 18.
To initialize the hardware:
I
Strap the system for one of the recommended power-up
configurations: maximum CPU frequency or minimum CPU
frequency setting. See “Safe Voltage and Frequency
Combination at Reset” on page 20 for details.
At reset, both the AMD-K6-2E+ and AMD-K6-IIIE+ low-
power processors drive 01010b on the VID[4:0] pins. The
VID-capable voltage regulator and implementation must be
equipped to handle this signaling at reset. See “Safe Voltage
and Frequency Combination at Reset” on page 20 for
details.
Logic AND gates should be used in conjunction with the
SPWRGD signal to ensure voltage continuity from the
voltage regulator at reset.
I
I
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