20
Hardware Implementation
AMD PowerNow! Technology Platform Design Guide for Embedded Processors
24267A/0—December 2000
Preliminary Information
Safe Voltage and Frequency Combination at Reset
A safe voltage and frequency combination at reset is a
combination that provides functional processor operation
conditions when RESET is negated.
Minimum Frequency
Initialization
Systems that strap the processor BF[2:0] inputs to 100b
configure the processor to boot with a core frequency of 2.0x
the processor bus frequency upon RESET, which is the lowest
supported frequency, are set for the
minimum
frequency
initialization.
I
The advantage to this implementation is that any supported
AMD-K6-2E+ and AMD-K6-IIIE+ processor core voltage can
be used for proper operation for the minimum frequency
setting with the BF multiplier of 2.0x.
The disadvantage of this method is that the maximum rated
frequency of the processor cannot be determined by the
state of the BF[2:0] pins.
I
C
onnecting the processor’s VID[4:0] outputs to the regulator’s
D[4:0] inputs through a multiplexer that selects the processor’s
VID[4:0] outputs when SPWRGD = 1 will result in a CPU
voltage of 1.5 V. If the processor’s VID[4:0] outputs are mapped
with a one-to-one correspondence to the regulator’s D[4:0]
inputs, it is required that the multiplexer drive 01010b to the
D[4:0] regulator inputs, respectively, when SPWRGD = 0. This
maintains V
CC2
continuity at 1.5 V for the core voltage as
SPWRGD transitions from unstable to good. The combination of
1.5 V and a 2.0x bus frequency multiplier provides a voltage and
frequency at power up that guarantees functional operating
conditions.
If the BF[2:0] inputs are strapped to select a 2.0x bus frequency
multiplier, but a higher performance level is desired before
loading the OS, then it is the responsibility of the BIOS or the
RTOS to adjust the processor’s core frequency and voltage to
the desired operational level early in the POST routine.