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| 型號(hào)： | 24267A |
| 英文描述： | Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors |
| 中文描述： | “AMD的K6E家庭”，“嵌入”，“處理器的AMD PowerNow??？技術(shù)平臺(tái)設(shè)計(jì)指南應(yīng)用指南“ |
| 文件頁(yè)數(shù)： | 32/50頁(yè) |
| 文件大小： | 957K |
| 代理商： | 24267A |
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26
Hardware Implementation
AMD PowerNow! Technology Platform Design Guide for Embedded Processors
24267A/0—December 2000
Preliminary Information
Gating PGOOD During a Voltage Transition
Most DC/DC regulators, such as the Maxim 1711, have an output
to indicate a stable core voltage (PGOOD) that may glitch low
during AMD PowerNow! technology voltage transitions.
PGOOD can be used by system logic to generate the SPWRGD
(system power good) signal. Because the south bridge asserts
CPURST when SPWRGD is negated, any glitches of PGOOD
during these state transitions must be intercepted in order to
prevent a CPU reset.
The recommended solution for intercepting PGOOD and
ensuring that a system reset does not occur during
AMD PowerNow! technology core voltage transitions is to
logically OR the PGOOD output with the PCIRST# signal.
However, since the regulator
’s PGOOD signal is gated, this
solution does not allow the system to monitor the CPU core
voltage for guarding against an out-of-spec condition.
Figure 6 on page 27 illustrates the necessary modifications for
intercepting the DC/DC regulator PGOOD signal
AMD PowerNow! technology voltage transitions.
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