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| 型號(hào)： | 24267A |
| 英文描述： | Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors |
| 中文描述： | “AMD的K6E家庭”，“嵌入”，“處理器的AMD PowerNow??？技術(shù)平臺(tái)設(shè)計(jì)指南應(yīng)用指南“ |
| 文件頁數(shù)： | 22/50頁 |
| 文件大小： | 957K |
| 代理商： | 24267A |
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16
Dynamic Core Frequency and Core Voltage Control
AMD PowerNow! Technology Platform Design Guide for Embedded Processors
24267A/0—December 2000
Preliminary Information
AMD PowerNow! Technology Initialization
Initialization of the AMD-K6-2E+ and AMD-K6-IIIE+ low-power
processors is straightforward. Below is a complete summary
illustrating the actions required to properly initialize these
processors for implementation of AMD PowerNow! technology.
Software
Initialization
Detailed information for effective software control of devices
enabled with AMD PowerNow! technology is provided in the
“Software Implementation” section, beginning on page 28.
To initialize the software:
I
Write the I/O base address (IOBASE) field (EPMR[15:4]) for
the 16-byte EPM I/O block. This sets up the location in the
I/O map where the EPM I/O block will reside. Be sure to
locate the EPM I/O block so that it does not conflict with
other system I/O-mapped resources. The EPMR is accessed
at MSR location C000_0086h.
Clear the Enable AMD PowerNow! Technology Management
(EN) bit (EPMR[0]) to disable address decodes of the EPM
I/O block fields. Clearing EPMR[0] ensures that errant
writes to I/O space do not accidentally change the
AMD PowerNow! technology state. For Windows desktop-
based operating systems, the SMI handler will set
EPMR[0]=1b only when SMM is entered for the purpose of
doing an AMD PowerNow! technology state transition. Real-
time operating systems should set EPMR[0]=1b only when
attempting an AMD PowerNow! technology state transition.
This bit may be cleared in the same MSR write that
initializes the EPM I/O block base.
Note:
EPMR[0] should be cleared upon completing any
AMD PowerNow! technology state transition to ensure errant
writes to I/O space do not inadvertently alter the
AMD PowerNow! technology state of the processor.
I
I
The VIDC bit (BVC[10]) should be set to 1 at power-on self
test (POST).
All subsequent writes to this field should
ensure that this bit equals 1b at all times.
Initializing this bit
causes a read/modify-bit/write operation on the BVC field.
After reading the BVC field and setting the VIDC bit during
initialization, be sure to clear all bits in the SGTC field
before writing the BVC field back out. This is required
because the data returned in the SGTC field is invalid, as it
is a write-only field.
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