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| 型號(hào)： | 24267A |
| 英文描述： | Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors |
| 中文描述： | “AMD的K6E家庭”，“嵌入”，“處理器的AMD PowerNow?。考夹g(shù)平臺(tái)設(shè)計(jì)指南應(yīng)用指南“ |
| 文件頁數(shù)： | 11/50頁 |
| 文件大?。?/td> | 957K |
| 代理商： | 24267A |
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Enhanced Power Management Features
5
24267A/0—December 2000
AMD PowerNow! Technology Platform Design Guide for Embedded Processors
Preliminary Information
IOBASE Field
The EPM 16-byte I/O block is located at the I/O address
specified by the IOBASE field and is initialized during power-
on self test (POST) by the BIOS or RTOS. The EPM 16-byte I/O
block is then used to access the EPM features.
The EPM features are hidden from all application software and
need only be accessible by an RTOS or an SMM handler for
Microsoft
operating systems. Therefore, the BIOS does not
need to report the I/O range to the operating system.
GSBC Bit
If the GSBC bit is enabled (set to 1), a special bus cycle is
generated once a dword access is made within the EPM 16-byte
I/O block. The EPM special bus cycle is defined by the processor
driving D/C# low, M/IO# low, W/R# high, BE[7:0]# to BFh and
A[31:3] to 0000h. The system logic must return BRDY# in
response to all processor special cycles.
EN Bit
The Enable AMD PowerNow! Technology Management (EN) bit
should only be enabled (set to 1) by the RTOS, BIOS, or SMM
handler when attempting to access the EPM features.
Upon exiting, the EN bit should be disabled to protect the EPM
16-byte I/O block from spurious activity. When the EN bit is
disabled, accesses to the EPM block 16-byte I/O block are
passed to the host bus.
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