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參數(shù)資料
| 型號： | 24267A |
| 英文描述： | Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors |
| 中文描述： | “AMD的K6E家庭”，“嵌入”，“處理器的AMD PowerNow！？技術平臺設計指南應用指南“ |
| 文件頁數(shù)： | 38/50頁 |
| 文件大小： | 957K |
| 代理商： | 24267A |
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32
Software Implementation
AMD PowerNow! Technology Platform Design Guide for Embedded Processors
24267A/0—December 2000
Preliminary Information
Event Sequence
for AMD PowerNow! Technology State Transitions
The following is a summary sequence of events outlining what
must occur for a successful AMD PowerNow! technology state
transition:
I
An SMM handler or BIOS or operating system function may
be called to carry out the AMD PowerNow! technology state
transition.
Set the ACPI-defined ARB_DIS bit in the north bridge to
prevent PCI and AGP bus masters from being granted the
bus
and
access
to
system
AMD PowerNow! technology state transition is taking place.
This is necessary because the processor is not capable of
responding to cache snoops while its core voltage and/or
frequency are being transitioned.
Note:
All bus activity to the processor must cease before initiating
the AMD PowerNow! technology state transition. This is
critical as a bus transaction may be in progress when the
ARB_DIS bit is set. Additionally, there may be several
memory accesses queued, which must be completed prior to
entering EPM Stop Grant State.
I
memory
while
the
I
Enable the EN bit of the EPMR register, making the
frequency and voltage control fields accessible within the
EPM 16-byte I/O block.
Write the desired values for the requested operating voltage
and frequency settings in the BVC field.
Initiate the AMD PowerNow! technology state transition by
writing a non-zero value to the SGTC field within the BVC
field of the EPM 16-byte I/O block. This action causes the
processor to enter the EPM Stop Grant state.
After the AMD PowerNow! technology state transition,
disable the EN bit of the EPMR register, which renders the
frequency and voltage control fields invisible within I/O
space.
Clear the ARB_DIS bit in the north bridge to allow system
memory accesses.
If an SMM handler is used to invoke EPM Stop Grant State, a
RSM instruction should be executed to return the CPU to
normal operation.
I
I
I
I
I
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