參數(shù)資料
型號: 21440
廠商: Intel Corp.
英文描述: Multiport 10/100Mb/s Ethernet Controller(多端口10/100Mb/s 以太網(wǎng)控制器)
中文描述: 多端口10/100Mb/s以太網(wǎng)控制器(多端口支持10/100Mbps以太網(wǎng)控制器)
文件頁數(shù): 83/92頁
文件大小: 1352K
代理商: 21440
21440 Multiport 10/100Mb/s Ethernet Controller
8-7
Electrical and Environmental Specifications
8.8
MII/SYM Port Specifications
The MII/SYM port electrical specifications are compliant with the IEEE 802.3 Standard.
8.8.1
DC Specifications
Table 8-13
lists the MII/SYM port DC specifications.
8.8.2
Signals Timing
This section describes the timing diagram of the MII/SYM port.
8.8.2.1
Clocks Specifications
Figure 8-5
shows the MII/SYM port clocks timing diagram.
Table 8-14
lists the MII/SYM port signals timing specifications.
Table 8-13. MII/SYM Port DC Specifications
Symbol
Parameter
Condition
Minimum
Maximum
Vih
Input high voltage
2 V
Vil
Input low voltage
0.8 V
Voh
Output high voltage
Ioh =
4 mA
2.4 V
Vol
Output low voltage
Iol = 4 mA
0.4 V
Ii
Input leakage current
15 μA
15 μA
Cin
Pin capacitance
5 pF
10 pF
Figure 8-5. MII/SYM Clock Timing Diagram
Table 8-14. MII/SYM Port Signals Timing Specifications
Symbol
Parameter
Minimum
Maximum
Fm10
tclk, rclk frequency in 10 Mb/s
2.5 MHz
100 ppm
2.5 MHz + 100 ppm
Fm100
tclk, rclk frequency in 100 Mb/s
25 MHz
100 ppm
25 MHz + 100 ppm
Tmc
tclk, rclk cycle time
Tmh
tclk, rclk high time
0.35
×
Tmc
0.65
×
Tmc
Tml
tclk, rclk low time
0.35
×
Tmc
0.65
×
Tmc
Vmh
tclk, rclk high threshold
2 V
Vml
tclk, rclk low threshold
0.8 V
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