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參數(shù)資料
| 型號(hào)： | 21440 |
| 廠商： | Intel Corp. |
| 英文描述： | Multiport 10/100Mb/s Ethernet Controller(多端口10/100Mb/s 以太網(wǎng)控制器) |
| 中文描述： | 多端口10/100Mb/s以太網(wǎng)控制器（多端口支持10/100Mbps以太網(wǎng)控制器） |
| 文件頁(yè)數(shù)： | 27/92頁(yè) |
| 文件大?。?/td> | 1352K |
| 代理商： | 21440 |
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21440 Multiport 10/100Mb/s Ethernet Controller
3-7
Register Descriptions
3.2.2.5
Receive Status Register
This register reports events that have occurred during packet reception. All bits are reset upon
reading this register. The bits in this register are set only if the receive logic is programmed to pass
packets with the corresponding event in the receive filtering mode register (RX_FILT_MOD). If a
packet with multiple errors is to be passed and not all the corresponding bits in the receive filtering
mode register (RX_FILT_MOD) are set, none of the bits in this register are set. The receive status
is also appended to the end of the packet in the receive FIFO.
Bit Name
Bit Number
Bit Description
FLC
7
Flow control packet.
Indicates that a flow-control packet was received.
—
6
RESERVED
MER
5
MII error.
Indicates either that a symbol error was detected in the SYM mode or that
an MII error signal was asserted in the MII mode during packet reception.
RTL
4
Too long packet.
Indicates that a packet longer than the maximum allowable size has been
received.
SRT
3
Short packet.
Indicates that a packet shorter than 64 bytes has been received.
DRB
2
Alignment error.
Indicates that a packet was received with CRC and framing errors.
CRC
1
CRC error.
Indicates that a packet was received with a CRC error but without a framing
error.
OVF
0
FIFO overflow.
Indicates that there was not enough space available in the receive FIFO
during packet reception.
Access Rules
Register access
R
Value after reset
00H
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